[trademark789]

Purpose

This change extends 1Cat's low-latency push all-reduce from fully connected
four-GPU NVLink groups to other connected NVLink and PCIe peer topologies.
It targets single-node tensor-parallel groups with NVLink, PCIe peer access,
or both, to reduce collective communication and synchronization time during
token generation.
Target layouts include two-GPU NVLink baseboards, mixed meshes, NVSwitch, and
PCIe peer connections through switches such as PLX/PEX.

At model load, the planner detects peer connections and chooses reduction
and transfer orders for the configured payloads. It compiles candidate
schedules into CUDA kernels, verifies their results, and measures complete
all-reduce calls against the group's current serving path. A schedule is
selected only when it is more than 1% faster. Cached selections are
requalified at startup.

The feature is opt-in and uses FP16 inputs, outputs, sums and partial
transfers by default. Optional FP32 sums and partial transfers reduce
accumulation rounding error at a possible conversion and communication cost.
Hardware coverage and remaining validation are listed under Test Result.

User impact

Latency and token generation

Latency columns show FP16 all-reduce at 5 KiB per rank: 2,560 elements at
two bytes each. TG columns estimate the gain from this change against the
current serving path, with speculative decoding held off or on in both runs.
The on column uses a four-token MTP scenario; neither column includes the gain
from enabling speculative decoding. All TG values are conditional workload
projections. Rows labeled untested also use assumed latency proxies.

Topology	Current default latency	Planned latency	TG Gain, SpecD/on	TG Gain, SpecD/off
NVLink pair	9.144–10.044 µs	3.732–3.824 µs	≈2–6%	≈3–10%
PCIe switch pair (PIX)	11.264 µs	4.648 µs	≈3–7%	≈4–10%
Mixed NVLink/PCIe, eight GPUs	21.819 µs	6.341 µs	≈6–15%	≈10–22%
Fully connected NVLink, four GPUs †	5 KiB unmeasured	Retained-path scenario	0% †	0% †
NVLink mesh, eight GPUs (untested *)	≈21.8 µs	≈6.3 µs	≈6–15%	≈10–22%
NVSwitch, two–four GPUs (untested *)	≈9.1–10.0 µs	≈3.7–10.0 µs	≈0–6%	≈0–10%
Cross-switch/socket PCIe pair with P2P (untested *)	≈22.5 µs	≈9.3 µs	≈5–13%	≈8–18%
No connected peer route	Existing path	Unchanged	0%	0%

SpecD means speculative decode, including
DFlash2 and MTP.

The first three latency rows are measured. The NVLink and PCIe pair baselines
use vLLM's single-stage peer-read all-reduce, with registered graph buffers;
the mixed eight-GPU baseline uses NCCL. The pair implementation reads peer
inputs directly and is separate from 1Cat's four-GPU NVLink push algorithm.
The measured PCIe path uses SXM2 V100s communicating over PCIe. Standard
V100 PCIe cards
are a target configuration and still need board-specific qualification.
The measured ranges for NVLink pairs cover three different connections.

Host-staged starting point. An earlier two-GPU PCIe model test, with
DFlash2 enabled, measured 87.47 tok/s before direct PCIe peer access worked
and 118.43 tok/s with direct peer-write reduction afterward: 35.4% higher
TG. Average decode time fell from 11.43 to 8.44 ms per emitted token, or
48.59 to 35.89 ms per speculative round. The same packed 27B model, launch
options and prompt produced identical 256-token outputs and 60 draft rounds.
The earlier run excluded PCIe peer access from NCCL; the later run followed
the IOMMU/ACS configuration changes and used direct PCIe push. This measures
that complete configuration change, rather than an algorithm change with
peer access already enabled. It used 10/80 KiB model reductions and an earlier
runtime; it is separate from the 5 KiB collective timings and conditional TG
projections here, and does not validate model throughput on this PR branch.

Reference workload. Each reduction row contains 2,560 FP16 elements
(5 KiB). Assume 128 eligible, non-overlapped target reductions per decode step.
Speculation uses four draft steps with 16 eligible 5 KiB reductions each,
followed by 128 target-verification reductions at 25 KiB (five rows).
Non-collective work is assumed to take 8–20 ms per ordinary
decode step or 24–60 ms per speculative round. Compute and acceptance are held
constant. These timing budgets and call counts are scenario inputs, not
measured model timings; the percentage ranges show sensitivity to those inputs.

The calculation is 100*((C + T_current)/(C + T_planned) - 1), where C is
non-collective time, T_off = 128*L_5KiB, and
T_on = 64*L_5KiB + 128*L_25KiB. Latencies use microseconds. The 25 KiB
inputs come from the corresponding measurements in the full tables below.
Fixed tokens emitted per speculative round cancel in the rate ratio. Both
columns use 100*(TG_planned/TG_current - 1) within their own decode mode;
the on percentage is independent of the off percentage. For example, a 6%
on gain means 106 tok/s if the current path with speculation already enabled
delivers 100 tok/s. Those rates illustrate the denominator, not a model result.

The on estimate uses the sequential MTP4 scenario above; DFlash2's parallel
drafting requires different workload inputs and is not separately estimated here.

Untested scenarios (*). These are analogy-based calculations, not
calibrated predictions for those fabrics:

• NVLink mesh: use the measured mixed eight-GPU latency pair as a proxy.
  A pure NVLink mesh, such as a
  DGX-1 cube mesh,
  may have a different default route and transfer cost.
• NVSwitch: use the measured NVLink-pair timings as proxies, with both
  faster-schedule and unchanged-current-path scenarios. The range represents
  those assumptions, not an established NVSwitch latency or improvement bound.
• Cross-switch/socket PCIe: assume both current and planned latency are
  twice the measured switch-pair latency at each payload, representing a
  two-stage peer-communication scenario. Actual hop cost and peer support
  need measurement; SYS alone does not establish either.

Retained-path scenario (†). The four-GPU control kept its current path at
10 KiB (4.612 µs). Its 5 and 25 KiB latencies were not measured in this run;
the 0% TG scenario assumes the current path is also retained at those sizes.

The full tables retain the six measured payloads and both precision modes.
For example, PCIe savings are 6.616 µs per call at 5 KiB and 9.648 µs at
25 KiB. Actual TG gains depend on the eligible call count, overlap, compute
budget and speculative acceptance of the model being served. Complete-model
TG measurements on the rebuilt branch remain pending.

Compatibility and costs

The feature is disabled by default. TP1 and multi-node TP retain their
current dispatch. Enabled groups tune configured, contiguous FP16 tensors
with 16-byte alignment. Unmatched sizes, dtypes and layouts use the original
dispatcher and precision behavior. All-gather, broadcast and existing
GEMM/RMSNorm fusions are unchanged.

Cold loads add CUDA compilation and profiling work; cached loads still
qualify the selection. Optional FP32 sums can add conversion and transfer
cost even when the comparison communicator is selected. Qualification errors
stop startup. Model-load overhead, model-output and token differences,
throughput on a complete rebuilt wheel, concurrent-group contention and
multi-stream reentrancy remain unverified.

Implementation

Profiling and selection

Selection runs at model load, independently for each enabled single-node TP
group and configured payload. Serving uses the installed result without
running a search during token generation.

flowchart TD
    A["Model load"] --> B["Discover topology and peer read/write capability"]
    B --> C["Derive model payloads and precision"]
    C --> D["Generate and rank reduction schedules"]
    D --> E{"Connected peer schedule available?"}
    E -- No --> F["Keep current serving path"]
    E -- Yes --> G{"Matching cached selection?"}
    G -- Yes --> H["Requalify cached selection"]
    G -- No --> I["Compile and qualify shortlist"]
    I --> J["Measure complete schedules and current serving path"]
    J --> K["Select extension only if more than 1% faster"]
    K --> L["Cache selection"]
    F --> M["Install dispatch before serving graph capture"]
    H --> M
    L --> M
    H -. Qualification error .-> X["Stop startup"]
    I -. Qualification error .-> X
    J -. Qualification error .-> X

Loading

Discovery maps GPU identities and usable bidirectional peer edges. The
planner tracks each rank's contributions and reduction dependencies, using
link type and reported PCIe generation/width for initial cost estimates.
These estimates rank candidates; they are not per-link measurements.

The default search budget is 2,048 with a shortlist of eight. Shortlisted
schedules are compiled, qualified and timed with automatic launch geometries.
The final comparison measures complete calls against the current serving
communicator under the same precision and serving-capture policy.
Users do not need a board-specific schedule or a manual reduction order.

Numerical qualification

Qualification changes inputs, poisons output buffers and checks dependent
results for stale or missing contributions. Compiled schedule kernels must
match their declared reduction expression bitwise. They share an exact
reference without extra CPU tensor collectives.

The current serving communicator can use a different reduction order
and round intermediate sums differently, particularly with three or more
ranks. Its qualification uses an accumulation-error bound so valid FP16
results can pass without matching a fixed FP32 reference bitwise. The bound is
gamma(n-1)*sum(abs(x)) + 2^-11*abs(sum(x)) + n*2^-25
against FP64 reference sums, with gamma(k)=k*u/(1-k*u). Here n is the number
of ranks and u is 2^-11 for FP16 accumulation or 2^-24 for the explicit
FP32 policy. The absolute-sum term accounts for cancellation; the remaining
terms cover FP16 output rounding. Checks of dependent calls exchange the
actual intermediate outputs to account for valid rounding differences.

Graph capture and timing

Qualification and timing enter the serving communicator's capture context,
allocate inputs under its CUDA IPC policy, and register graph buffers before
replay. The registered-buffer path avoids the input copy used by its
staging-buffer path. Including the copy in a serving comparison would
overstate the current serving path's latency and could select a slower schedule.

Startup, cache and teardown

Setup finishes before model compilation and serving graph capture. Cache
identity includes payload, precision, topology, source and loaded native
libraries. Cached selections are requalified. IPC channels close before the
CPU process group is destroyed. Planning and tuning run only during setup.

Related work

PR #963 tunes the fixed TP4 push
kernel; PR #1208 handles graph
input IPC export; PR #1219
verifies peer access for compact collectives; and
PR #1216 provides a host-memory
path for two GPUs without peer access.

Test Plan

From a built checkout of this PR, with development dependencies installed:

.venv/bin/python -m unittest discover \
  -s tests/distributed/topology_all_reduce -t . -v
.venv/bin/python -m tools.generate_architecture_reference --check
.venv/bin/python -m tools.config_inventory --check
pre-commit run --from-ref 6f3557c973b4602905037e086fd4acba9b0d867f --to-ref HEAD

The CPU suite covers contribution tracking, disconnected graphs and relays,
nonconsecutive device IDs, both precisions, cache invalidation, selection
margins, startup payload sizing, fallback and IPC cleanup. Numerical tests
include valid FP16 rounding at 3–64 ranks, cancellation, missing contributions
and non-finite values. Capture tests require buffer registration before replay.

The collective benchmark discovers representative peer pairs and measures
those pairs plus the complete visible group. Use a new output directory for
each run; it writes per-rank JSON measurements and checks both cold selection
and cached requalification. Set the process count to the number of visible
GPUs on one host:

.venv/bin/python -m torch.distributed.run --standalone --nproc-per-node 8 \
  benchmarks/kernels/benchmark_topology_all_reduce.py \
  --sizes-kib 1 5 10 25 40 80 --precisions fp16 fp32 \
  --output topology-all-reduce-results

Repeat the larger-payload full-group probes with:

.venv/bin/python -m torch.distributed.run --standalone --nproc-per-node 8 \
  benchmarks/kernels/benchmark_topology_all_reduce.py --groups full \
  --sizes-kib 128 256 512 --precisions fp16 --output topology-large-fp16
.venv/bin/python -m torch.distributed.run --standalone --nproc-per-node 8 \
  benchmarks/kernels/benchmark_topology_all_reduce.py --groups full \
  --sizes-kib 128 256 384 448 512 --precisions fp32 --output topology-large-fp32

For the controls, set TP3_GPUS to three GPU indices and TP4_NVLINK_GPUS
to four GPUs with a fully connected NVLink topology. To reproduce the NCCL
control, choose a three-GPU group whose ordinary dispatcher uses NCCL.
The specific indices depend on the host:

CUDA_VISIBLE_DEVICES="$TP3_GPUS" \
.venv/bin/python -m torch.distributed.run --standalone --nproc-per-node 3 \
  benchmarks/kernels/benchmark_topology_all_reduce.py --groups full \
  --sizes-kib 10 --precisions fp16 --output topology-control-tp3
CUDA_VISIBLE_DEVICES="$TP4_NVLINK_GPUS" \
.venv/bin/python -m torch.distributed.run --standalone --nproc-per-node 4 \
  benchmarks/kernels/benchmark_topology_all_reduce.py --groups full \
  --sizes-kib 10 --precisions fp16 --output topology-control-tp4

Remaining serving validation: rebuild the complete wheel; compare the enabled
and disabled configurations with the same model and request workload. Measure
cold/cached model-load time, output and token differences, request kernel
profiles and throughput for both precision modes. Repeat changed-input graph
replay, concurrent TP groups and supported layouts beyond the test host.

Path coverage

Path / provider	Format	Key conditions (shape, TP/EP, graph, capability)	Expected selection / fallback	Evidence (source / static / executed / measured)	Unverified scope
Compiled CUDA IPC schedules	FP16 input/output; FP16 or FP32 partials	Single-node TP, connected peer graph; plan limit 64 devices	Measured schedule or comparison dispatcher	42 CPU tests and 70 completed GPU configurations	Complete rebuilt-wheel model execution; NVSwitch and other GPU generations
Startup selection and dispatch	Configured contiguous FP16 payloads, 16-byte alignment	Before model compilation/capture; target/draft widths and speculative token counts	Extension only when more than 1% faster; original dispatch for other signatures	CPU startup tests; cold and cached GPU qualification	Batched-prefill widths outside configured sizes; concurrent TP/PP/EP tuning; multi-stream reentrancy
Cache and teardown	Same payload, precision, topology and runtime identity	IPC cleanup while CPU group remains alive	Requalify cached selections; invalidate on identity changes	CPU identity/lifecycle tests; GPU cached qualification	Full-model lifecycle and failure recovery
TP1, multi-node and unsupported signatures	Existing formats	No communicator, multi-node TP or unmatched operation signature	Original dispatch	CPU tests	Multi-node model execution; no network transport added

Acceleration and benchmark contract (required for performance changes)

• Default enabled or opt-in: Opt-in, disabled by default.
• Required CLI options and environment switches: Add
  --kernel-config '{"topology_all_reduce":{"enabled":true}}' to a single-node
  TP serving command. Select FP32 with
  --kernel-config '{"topology_all_reduce":{"enabled":true,"precision":"fp32"}}'.
  Requires Linux CUDA IPC, usable peer mappings, nvidia-smi, and a CUDA/Ninja
  compilation toolchain. No new environment switches.
• KV cache dtype used for the benchmark: Not applicable. These are collective
  benchmarks with synthetic FP16 activations; no model, weights or KV cache.
• Wheel SHA or source commit: Tested files match public PR commit
  cc1ab729.
  CUDA kernels generated by the extension and the existing collective provider
  were rebuilt from the tested sources. Other installed native runtime binaries
  were reused. A complete rebuilt wheel has not been tested.
• PYTHONPATH, source overlays, or external native libraries used: The
  benchmark imports this PR's Python source and JIT-compiles its schedules.
  The existing collective provider was rebuilt separately to match its expected
  API; the remaining installed native runtime was reused. There is no external
  kernel-library dependency in the submitted implementation.
• User-entry route-hit, speed, and output-quality evidence: Pending for this
  branch. The completed GPU tests measure and qualify collectives, including
  dependent graph replay; they do not establish model throughput or output parity.
• Existing kernel/backend registry and capability-rejection reasons: Uses
  CudaCommunicator.all_reduce and preserves its original bound method.
  Compiled schedules need a connected peer graph and a matching tensor
  signature. TP1 and multi-node TP skip installation. Plans above 64 devices
  and invalid launch/payload widths are rejected. Qualification errors stop
  startup. Existing compute/communication fusions are unchanged.
• Per-engine configuration and deprecated-variable compatibility:
  KernelConfig.topology_all_reduce contains enabled, precision and
  cache_dir. Precision defaults to fp16. The configured precision applies
  to tuned signatures, including the comparison communicator; unmatched
  signatures retain their original behavior. Enabled computation policy is
  included in the configuration hash; cache location is excluded. No deprecated
  variables change meaning.
• New/changed environment metadata and generated reference check: No new
  VLLM_* variables. Generated configuration and runtime references are updated;
  architecture and ownership checks pass.
• Route snapshot command and intentional changed rows: No compute-provider
  snapshot change. tools/sm70_route_snapshot.py covers compute providers;
  this change selects collective schedules. The benchmark records method
  choices and per-rank measurements. Request kernel profiling remains pending.
• SM70 registered variables / unregistered reads / model-parameter restrictions,
  before -> after: VLLM_SM70_* registered names: 472 -> 472; all registered
  names: 1005 -> 1005. New unregistered VLLM_* reads: 0 -> 0. Model-name
  restrictions introduced by this change: 0 -> 0.

Test Result

• 42 CPU tests passed. Formatting, typing, architecture, layering,
  configuration and ownership checks passed.
• 70 GPU configurations completed qualification and cached requalification
  on every participant: 60 pair/full-group configurations, two controls and
  eight larger-payload configurations. Results below include completed cells
  only. A separate ten-configuration run passed through the public benchmark
  CLI; its duplicate timings are excluded.
• Hardware/software: eight Tesla V100-SXM2-16GB GPUs (SM70), NVLink and PCIe peer
  connections, driver 580.105.08, PyTorch 2.10.0+cu128, CUDA 12.8, NCCL 2.27.5.
  No clock changes were made for the benchmark.
• Three-rank NCCL qualification passed with valid FP16 intermediate rounding.
  The four-rank NVLink control exercised the current registered-buffer path and
  retained it as the lower-latency method.
• Full-model output, throughput, startup overhead and complete rebuilt-wheel
  execution remain unverified. NVSwitch and standalone PCIe-without-peer-access
  hardware latency were not measured.

Comparison methods

The tables compare the extended 1Cat all-reduce with the same group's
comparison communicator, under the requested precision policy.

For NVLink and PCIe peer pairs, the comparison is vLLM's single-stage peer-read
all-reduce (cross_device_reduce_1stage), using registered graph buffers.
Two-GPU groups are supported by this implementation. The separate 1Cat push
kernel requires a fully connected four-GPU NVLink group on SM70. The mixed
eight-GPU comparison uses NCCL.

• FP16 rows: FP16 input/output with the comparison communicator's normal
  FP16 serving behavior.
• FP32 rows: FP16 input/output, FP32 sums and partials. The comparison
  communicator receives FP32 tensors and converts the result back to FP16.
  Its timing includes both conversions and the FP32 reduction. The FP32
  table compares both implementations with this policy enabled; ordinary
  FP16 serving timings are in the FP16 table.

At every tested size of 1, 5, 10, 25, 40 and 80 KiB, the extension had lower
latency than the stated comparison communicator on every tested pair and the
mixed eight-GPU group, in both precision modes.

The four-GPU NVLink control at 10 KiB retained its current serving path:
4.612 µs versus 4.736 µs for the extension.

Connection category	Meaning	Measured coverage
NVLink	Direct GPU-to-GPU communication over NVLink	Three two-GPU configurations, six payloads, both precisions
PCIe peer	Direct peer-memory access over a PCIe switch (PIX)	One two-GPU configuration, six payloads, both precisions
PCIe without peer access	No usable direct GPU peer-memory path	No standalone hardware latency result; CPU tests cover disconnected graphs and fallback
Mixed eight-GPU topology	Collective uses both NVLink and PCIe peer connections	Six payloads, both precisions, plus larger-payload probes

PCIe path descriptions use NVIDIA's nvidia-smi topo -m labels:

Description	NVIDIA label	Connection path
PCIe through up to one bridge	PIX	At most one PCIe bridge
PCIe through multiple bridges	PXB	Multiple PCIe bridges, without crossing the host bridge
PCIe through the CPU host bridge	PHB	PCIe and a PCIe host bridge
PCIe within one NUMA node	NODE	PCIe and the interconnect between host bridges within one NUMA node
PCIe across NUMA nodes	SYS	PCIe and the CPU interconnect between NUMA nodes

Peer read/write capability is checked separately; SYS alone does not mean
peer access is unavailable. The table is a naming reference, not additional
hardware coverage. See
NVIDIA's topology definitions.
A missing direct edge can be bridged through other peer-accessible GPUs. A
group with no connected peer route retains its current dispatcher.

Latency by payload size

Payload is the original FP16 activation size per rank (1 KiB = 1,024 bytes).
Each cell is extended 1Cat all-reduce / comparison communicator latency in
microseconds; bold marks the selected method. NVLink entries show the
minimum–maximum latency across three measured configurations, separately for
each implementation. The extension was selected for each configuration.

Measurements use the serving selector's search budget of 2,048, a shortlist
of eight and automatic launch geometries. Each result is the median of nine
samples after three warmups. A sample is the slowest rank's external-event
time per complete dependent collective call; an untimed readiness collective
precedes it. Numerical checks and CPU collectives are outside the timed GPU
events. No empty-control time is subtracted. These are complete collective
latencies, including synchronization.

Default FP16 sums and transfers:

Connection / group	Comparison path	1 KiB	5 KiB	10 KiB	25 KiB	40 KiB	80 KiB
NVLink (two GPUs)	vLLM peer-read all-reduce	3.492–3.804 / 8.720–9.824	3.732–3.824 / 9.144–10.044	3.636–3.904 / 9.660–10.480	3.864–4.184 / 12.056–12.280	3.956–4.408 / 12.524–12.976	4.168–5.288 / 12.248–13.380
PCIe peer, single-switch path (PIX, two GPUs)	vLLM peer-read all-reduce	3.948 / 10.672	4.648 / 11.264	5.360 / 13.604	7.536 / 17.184	9.780 / 19.296	16.188 / 26.840
Mixed NVLink + PCIe (eight GPUs)	NCCL	5.879 / 21.550	6.341 / 21.819	7.122 / 27.863	9.582 / 31.474	12.567 / 36.338	19.342 / 38.688

Optional FP32 sums and partial transfers, with the comparison conversions
described above:

Connection / group	Comparison path	1 KiB	5 KiB	10 KiB	25 KiB	40 KiB	80 KiB
NVLink (two GPUs)	vLLM peer-read all-reduce	3.668–3.744 / 13.716–14.268	3.808–4.020 / 14.840–15.260	3.868–4.036 / 15.904–15.984	4.120–4.192 / 16.996–17.424	4.072–4.512 / 17.188–18.092	4.132–5.140 / 17.744–19.848
PCIe peer, single-switch path (PIX, two GPUs)	vLLM peer-read all-reduce	4.040 / 15.624	4.784 / 18.288	5.284 / 20.100	7.608 / 26.220	9.880 / 31.700	16.336 / 46.832
Mixed NVLink + PCIe (eight GPUs)	NCCL	6.642 / 23.575	9.083 / 29.678	11.762 / 31.826	19.557 / 39.749	29.193 / 38.985	49.765 / 66.999

The extension keeps original inputs in FP16 and partial sums in FP32 when
requested. Measured two-rank FP32 schedules exchange only original FP16 inputs
and sum locally, so their transfer volume does not grow. Multi-stage schedules
can exchange FP32 partials, doubling the bytes for those partial transfers.

At 80 KiB, extended FP16 pair latency is 4.168–5.288 µs across the tested
NVLink configurations, versus 16.188 µs for the PCIe peer path. At 1 KiB,
those values are 3.492–3.804 µs and 3.948 µs. The PCIe result increases more
with payload size; these timings include the full collective.

Mixed eight-GPU larger-payload results, extended 1Cat all-reduce / NCCL in
microseconds:

Precision	128 KiB	256 KiB	384 KiB	448 KiB	512 KiB
FP16	26.126 / 54.318	46.921 / 95.849	not tested	not tested	90.373 / 165.070
FP32	70.807 / 95.611	136.933 / 165.600	202.418 / 207.945	233.211 / 229.161	273.733 / 251.049

Payload crossover

• NVLink and PCIe peer pairs: the extension was faster at every tested
  size from 1–80 KiB, for both precisions. Larger pair payloads were not measured.
• Mixed eight-GPU group, FP16: the extension was faster at every measured
  size from 1–512 KiB.
• Mixed eight-GPU group, FP32: the extension won at 384 KiB (202.418 µs
  versus 207.945 µs NCCL). NCCL won at 448 KiB (229.161 µs versus 233.211 µs)
  and 512 KiB. The observed change in selected method is between the 384 and
  448 KiB samples. Selection uses the 1% margin described above.

These are measured points on one system. The tests do not establish an exact
threshold or a crossover for the configurations where the extension remained
faster.

---

PR checklist

• Purpose, affected users and related PRs described.
• Test commands and comparison methods provided.
• Completed tests and remaining validation listed.
• Generated configuration and runtime references updated.

Contribution guidance:
vLLM contributing guide and
1Cat development guide.

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[Leonccaa]

Some feedback from running 1Cat-derived code on 4× V100 32GB PCIe behind a single PEX switch. The topology-adaptive approach (discover the peer graph, generate and qualify schedules, keep them only when they beat the current path) is a nice generalization of the fully connected TP4 kernel, and the qualification work (poisoned outputs, dependent replay, the explicit error bound, registered-buffer baselines) is really careful. Three things I think would help it land:

1. An end-to-end number. The TG gains are currently projections from collective latency. Each call saves a few microseconds against a decode step of several milliseconds or more, and some calls never reach the patched method: all_reduce_sum2 and the SM70 TP2/TP4 fused all-reduce + Gemma RMSNorm paths call ca_comm directly and keep the old kernels. One measured enabled/disabled TG comparison on a real model, together with the number of route hits per step, would be the strongest evidence for reviewers.
2. A smaller first step. The clearest win in your tables is the two-GPU pair (NVLink or PCIe peer), roughly 9–11 µs down to about 3.7–4.6 µs at 5 KiB. Landing that case first, with the general planner as a follow-up, would be much easier to review than a single 4,000-line change.
3. The right baseline on 4-GPU PCIe switches. Upstream treats 4-GPU PCIe as not fully connected, so the planner would be compared against NCCL there, but the TP4 push kernel also works over switch P2P. We run it in production in ReVolta (our SM70 fork of 1Cat) on that topology, in CUDA graphs up to 80 KiB, so for that build the baseline that matters is the push kernel. Also, in full-model runs on the same machine, raising the one-shot custom all-reduce cap from 80 KiB to 512 KiB made 3–8-way concurrent decode 3–12% slower than NCCL, so on PCIe the large-payload crossover may come earlier than on your mixed 8-GPU group.

We haven't run this branch on GPU yet, but we're happy to run the collective benchmark on our 4× PCIe-switch machine and post the results here.

[Leonccaa]

Thanks again for this PR. It prompted us to measure every all-reduce our engine actually issues, on both topologies, and that turned up something worth fixing.

What we measured. We recorded every all-reduce the engine issues while serving (MTP4 and DFlash2, one to eight concurrent requests), then replayed each call shape without the model and timed every available implementation at each payload: our custom kernels (push, one-stage, two-stage), PyNccl and torch NCCL, plus NCCL with NCCL_PROTO=LL and with NCCL_ALGO=Ring. Every cell was checked for correctness. Machines: our 4 × V100 32 GB PCIe behind one switch, and a rented 4 × V100-SXM2 32 GB with NVLink between every pair (a mix of NV1 and NV2 links), both at 250 W, FP16 [T, 2560].

PCIe switch. The routes we already ship are the fastest available at every payload the workload produces. What remains is a few eager (non-graph) calls, worth about 0.05–0.16 ms per step.

NVLink. Up to 16 tokens per call (80 KiB), the custom push kernel takes 4.4–7.7 µs against 16–21 µs for NCCL. Above that, only 32 and 64 tokens have fast paths (11.2 and 18.9 µs). At the other sizes from 20 to 56 tokens, the call falls back to the generic one-stage kernel: 17–22.5 µs for an all-reduce and 22–48 µs for the fused sum2 variant, about the same as or slower than NCCL (19–24 and 21–28 µs). MTP4 at four to eight concurrent requests and DFlash2 at three to eight issue about 48 of each per step at exactly these sizes, so sending them to NCCL is estimated to save about 0.7 ms per step at eight requests (0.67–0.70 ms over four rounds). NCCL's own protocol and algorithm switches gave nothing, because NCCL already uses Ring with LL at these sizes. We plan to fix this in ReVolta 0.1.5 and measure it end to end.

Where we landed on the design question. The decisions turned out to be few and fixed: the payload sizes follow from the token counts and the hidden size, and on each topology the best route changes at one or two thresholds. So for us, an offline probe that writes a small rule table for each topology fits better than choosing routes inside the engine at startup: no tuning time at startup, the same route (and therefore the same reduction order and output) on every run, and much less code to qualify. A planner like yours could still be the way to generate candidate schedules for unusual topologies, such as partial NVLink inside an 8-GPU group; a probe can measure those once and hand the result to the engine. Happy to compare notes on that split.

Still open on our side. In our last comment we offered to run your collective benchmark on our 4× PCIe-switch machine and post the results here. We have not done that yet; the numbers above come from our own tool. We will run benchmarks/kernels/benchmark_topology_all_reduce.py from this branch in our next GPU window and post the results. Our probe tool is not public yet; once it is, we will link it here in case it helps on other machines.

[Leonccaa]

As promised, we ran this branch's collective benchmark on our 4 × V100 32 GB PCIe machine (all four GPUs behind one PCIe switch, P2P on). Short version: your generated kernels are clearly faster than what we ship on this topology, which corrects what we wrote in our last comment.

How we ran it. benchmarks/kernels/benchmark_topology_all_reduce.py from 205ac6f550, unchanged, with only the topology_all_reduce package copied into a throwaway container of our 0.1.4 release image (nothing else changed, no network). planned_reduce.cpp JIT-compiled for sm_70 without warnings. FP16, --groups full pairs, --budget 2048 --shortlist 8, 13 payload sizes (1, 5, 10, 20, 25, 40, 80, 100, 120, 160, 200, 240 and 320 KiB, i.e. 1 to 64 tokens of a [T, 2560] FP16 hidden state plus your defaults), a 250 W power limit on every GPU (set and read back before the run), NCCL_GRAPH_REGISTER=0. Every cell came back measured with correct: true; the whole run took about 15 minutes.

Full group (4 GPUs), median of the 9 samples, µs per all-reduce:

KiB	tokens	your native	existing (our dispatch, measured by your tool)	native / existing
1	–	4.48	4.23	1.06
5	1	5.38	5.89	0.91
10	2	6.02	7.17	0.84
20	4	7.17	9.73	0.74
40	8	10.37	15.11	0.69
80	16	17.54	28.03	0.63
100	20	21.12	40.32	0.52
160	32	30.46	55.55	0.55
240	48	44.67	82.05	0.54
320	64	55.43	86.14	0.64

On the two-GPU pairs (PIX and PXB) native was 2 to 3 times faster than existing at every size (for example 10.37 against 22.53 µs at 80 KiB on the PIX pair).

Cross-check with our own tool. Your existing column measures our 0.1.4 dispatch (custom all-reduce up to 80 KiB inside a graph, PyNccl above). It came out 5–15 % above what our own sweep measured for the same dispatch on the same machine two days earlier (for example 28.03 against 26.85 µs at 80 KiB, 86.14 against 78.74 µs at 320 KiB), so we compare native against existing within your tool rather than against our numbers. Even with that offset, native is ahead from 2 tokens up, by 25–45 % from 4 to 64 tokens.

Correction. In our last comment we wrote that on the PCIe switch our shipped routes were the fastest available at every payload. That was true only among the implementations our sweep knew (our custom kernels and NCCL); your planned kernels beat all of them on this topology. Our NVLink finding held on the machine we measured it on, which mixes one- and two-link pairs; on a second NVLink machine with two links between every pair, our custom kernels stayed faster than NCCL up to about 60 tokens, so the best custom/NCCL cut-off depends on the link layout. That fits your topology-aware approach.

What we will do with it. These are isolated collective timings; we have not yet measured what they mean per decode step or for output determinism in serving. We will look at it after our 0.1.5 release and report back here. Raw results (rank files, receipts, the exact container command) are available if useful.

Thanks for the benchmark and the planner. It found something real on our hardware.