Design Verification using SystemVerilog

SystemVerilog builds on top of Verilog, enhancing readability and reusability. It introduces improvements primarily aimed at advanced verification and C language integration. The SystemVerilog Language Reference Manual (LRM) provides a detailed and comprehensive overview of the language’s capabilities and enhancements.

Folder Structure

Projects
.
├── FPGA_Projects
│   └── SV
│       ├── Readme.org
│       ├── sv_tcl_script
│       │   ├── sv_cstrs.tcl
│       │   └── sv_run.tcl
│       ├── sv_templates
│       │   ├── constraints
│       │   └── design
│       └── sv_verification
│   
└── Python_Scripts
    └── sv_scripts
        ├── sv_clean.py
        ├── sv_cstrs_design.py
        ├── sv_cstrs_run.py
        ├── sv_design.py
        └── sv_run.py

Clone Project

• Clone the repository SystemVerilog_Verification and place it according to the specified folder structure.

git clone https:/https://github.com/24x7fpga/SV.git ~/Projects/FPGA_Projects/

• Clone the Python_Scripts repository and place it according to the specified folder structure. While the repository contains various scripts, only the sv_scripts folder is required for running verification simulations.

git clone https://github.com/24x7fpga/Python_Scripts.git ~/Projects/

• Add the script location to your PATH.

echo 'export PATH=$HOME/Projects/Python_Scripts/sv_scripts:$PATH' >>~/.zshrc

Note: The PATH is a list of directories that your operating system searches through whenever you run a command, helping it locate the necessary executable files. On most Linux distributions, bash is the default shell, but choose the shell that you use.

Design Directories

• sv_verification: This repository is dedicated to SystemVerilog-based verification techniques. Concepts such as mailboxes, SV methodology, and testbench automation are demonstrated. Scripts and examples are provided to aid learning and implementation in practical verification scenarios. The repository homepage can be found here.
• cstrs_challenges: This repository is focused on mastering SystemVerilog constraints. It includes a collection of challenges and questions designed for practicing and improving constraint-writing skills. Examples and exercises are provided to enhance understanding. The repository homepage can be found here

Verification Basics

• Associative Arrays
• Automatic Task
• Break and Continue
• Class Example
• Constraint: Array Randomization
• Constraint: Bidirectional and Conditional
• Constraint: Weighted Distribution
• Constraint: Implication and Equivalence
• Constraint: In-line and External
• Constraint: Inside Operator
• Constraint: Solve-Before
• Deep Copy
• Do while Loop
• Dynamic Arrays
• For Loop
• Foreach Loop
• Forever Example
• Fork Join
• Fork Join Any
• Fork Join Disable
• Fork Join Wait
• Function Example
• Inheritance
• Method Outside Class
• Packed and Unpacked Array
• Polymorphism
• Queue
• Repeat Example
• Shallow Copy
• Static Task
• Super Keyword
• Task Example
• This Keyword
• Type Enumeration
• Virtual Keyword
• While Loop

Basic Examples

• Half Adder
• Full Adder

Verification Examples

• Adder Subtractor