Fix two critical firmware bugs: RISC-V interrupt CSR and TIM1 CH2 PWM config

[Copilot]

Two bugs in the untested CH32V003 firmware that would prevent it from compiling or running correctly.

Bug 1 — Wrong CSR in interrupt helpers (primask → mstatus)

irq_lock/irq_restore used ARM Cortex-M's primask register — this doesn't exist on RISC-V and causes a compile error. Fixed to use RISC-V mstatus with the MIE bit (bit 3) via an atomic csrrci/csrsi pair.

// Before (ARM-only, won't compile on RISC-V):
__asm__ volatile("csrr %0, primask" : "=r"(prev));
__asm__ volatile("csrc primask, 1");
// Restore checked prev & 1

// After (correct RISC-V):
__asm__ volatile("csrrci %0, mstatus, 8" : "=r"(prev));  // atomic read+clear MIE
// Restore checks prev & 0x8

Bug 2 — TIM1 CH2 configured via wrong register (CHCTLR2 → CHCTLR1 upper byte)

TIM1->CHCTLR2 was written to set up Fan 2's PWM output. On CH32V003, CHCTLR2 maps to channels 3 & 4 — channel 2 lives in the upper byte of CHCTLR1. Fan 2 (PD6) was left in reset "frozen" mode, producing no PWM signal.

// Before — accidentally configures CH3, leaves CH2 in frozen mode:
TIM1->CHCTLR1 = (6 << 4) | (1 << 3);          // CH1 only
TIM1->CHCTLR2 = (6 << 4) | (1 << 3);          // CH3 (wrong!)

// After — both channels in their correct register:
TIM1->CHCTLR1 = ((6 << 4) | (1 << 3))         // CH1: lower byte
              | (((6 << 4) | (1 << 3)) << 8);  // CH2: upper byte

Original prompt

read read me for context, review this untested firmware, if you see anything wring, make pr to fix

The user has attached the following file paths as relevant context:

• README.md
• fanControl\fanControl.ino

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