Add ai agent instructions and QEMU support

.devcontainer/ubuntu-24.04/Dockerfile

@@ -22,6 +22,7 @@ RUN apt-get update && \
         llvm-18-tools \
         locales \
         nano \
+        qemu-system-arm \
         software-properties-common \
         sudo \
         unzip && \
@@ -39,6 +40,7 @@ RUN apt-get update && \
 ENV LANG=en_US.UTF-8
 ENV LC_ALL=en_US.UTF-8
 ENV VIRTUAL_ENV=/opt/cmsis-python
+ENV VCPKG_DOWNLOADS=/var/cache/vcpkg
 ENV PATH="${VIRTUAL_ENV}/bin:${PATH}"
 
 RUN python3.14 -m venv "${VIRTUAL_ENV}" && \
@@ -60,8 +62,8 @@ RUN userdel --remove ubuntu && \
     echo "${USERNAME} ALL=(root) NOPASSWD:ALL" > "/etc/sudoers.d/${USERNAME}" && \
     chmod 0440 "/etc/sudoers.d/${USERNAME}"
 
-RUN mkdir -p /workspaces && \
-    chown "${USERNAME}:${USERNAME}" /workspaces
+RUN mkdir -p /workspaces "${VCPKG_DOWNLOADS}" && \
+    chown "${USERNAME}:${USERNAME}" /workspaces "${VCPKG_DOWNLOADS}"
 
 COPY vcpkg-configuration.json /home/
 COPY postCreateCommand.sh /home/

.devcontainer/ubuntu-24.04/devcontainer.json

@@ -9,6 +9,7 @@
     "remoteUser": "${localEnv:USER}",
     "mounts": [
       "source=${devcontainerId}-home,target=/home/${localEnv:USER},type=volume",
+      "source=cmsis-6-vcpkg-cache,target=/var/cache/vcpkg,type=volume",
       "source=${localEnv:HOME}${localEnv:USERPROFILE}/.ssh,target=/home/${localEnv:USER}/.ssh,type=bind,consistency=cached",
       "source=${localEnv:HOME}${localEnv:USERPROFILE}/.armlm,target=/home/${localEnv:USER}/.armlm,type=bind,consistency=cached",
       "source=${localEnv:HOME}${localEnv:USERPROFILE}/.iarlm,target=/home/${localEnv:USER}/.iarlm,type=bind,consistency=cached"

.devcontainer/ubuntu-24.04/postCreateCommand.sh

@@ -1,5 +1,13 @@
 #!/bin/bash
 
+VCPKG_CACHE_DIR="${VCPKG_DOWNLOADS:-/var/cache/vcpkg}"
+
+echo "Preparing shared vcpkg cache at ${VCPKG_CACHE_DIR} ..."
+sudo mkdir -p "${VCPKG_CACHE_DIR}"
+if [ "$(stat -c '%u' "${VCPKG_CACHE_DIR}")" -ne "$(id -u)" ]; then
+    sudo chown -R "$(id -u):$(id -g)" "${VCPKG_CACHE_DIR}"
+fi
+
 echo "Installing oh-my-bash ..."
 bash -c "$(curl -fsSL https://raw.githubusercontent.com/ohmybash/oh-my-bash/master/tools/install.sh)" --unattended
 sed -i 's/OSH_THEME="font"/OSH_THEME="powerline"/' ~/.bashrc

.gitignore

@@ -22,3 +22,4 @@ output
 linkchecker-out.csv
 .DS_STORE
 *.tmp
+.qlty

AGENTS.md

@@ -0,0 +1,37 @@
+# Repository agent instructions
+
+## Test verification
+
+- Run CMSIS-Core tests in the Ubuntu 24.04 dev container. Do not install test
+  dependencies on the host.
+- Read [`TESTING.md`](TESTING.md) before selecting or running tests. It contains
+  the container setup, matrix syntax, supported values, and license caveats.
+- Inspect the diff and run the smallest matrix that exercises the changed code.
+  Do not run the complete matrix by default. Documentation-only changes do not
+  require firmware tests unless they alter commands or test configuration.
+- When CMSIS tests are relevant, select at least an affected core, a compiler,
+  and an optimization level. Start with GCC and `none` unless the change points
+  to a different combination.
+- Expand the selection when applicable:
+  - Add Clang for shared compiler abstractions, intrinsics, or inline assembly.
+  - Add AC6 for Arm Compiler-specific paths when the required license is
+    available.
+  - Add `speed`, `size`, or all optimization levels for code-generation or
+    optimization-sensitive changes.
+  - Add secure and non-secure variants for TrustZone changes.
+  - Add representative M-profile generations for shared Core-M changes.
+  - Add the affected A-profile or R-profile core for Core-A or Core-R changes.
+  - Run CoreValidation `build run` when runtime behavior, startup, system,
+    exception, interrupt, or security behavior may have changed.
+- Quote wildcard selectors such as `-d "CM33*"` so the shell does not expand
+  them. Repeat `-c`, `-d`, or `-o` to select multiple values.
+- Build a CoreValidation configuration before running it. `build run` is the
+  preferred form for a fresh verification.
+- If a requested compiler, model, or core is blocked by a missing tool or
+  license, record the exact blocker and continue with the other relevant
+  configurations. Do not report an environment blocker as a source failure.
+- Before handoff, report the exact commands and matrix combinations run, their
+  pass/fail/skip totals, any filtered or blocked combinations, and whether the
+  worktree gained generated files.
+- Preserve pre-existing worktree changes. Remove only generated files created
+  by the current test run, after confirming their paths with `git status`.

CMSIS/CoreValidation/Layer/Target/CA9QEMU/Config/mem_ARMCA9.h

@@ -0,0 +1,35 @@
+/**************************************************************************//**
+ * @file     mem_ARMCA9.h
+ * @brief    QEMU vexpress-a9 memory regions used by the linker and MMU
+ ******************************************************************************
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/* Copyright (c) 2026 Arm Limited. All rights reserved. */
+
+#ifndef __MEM_ARMCA9_H
+#define __MEM_ARMCA9_H
+
+/* QEMU vexpress-a9 high memory starts at 0x60000000. */
+#define __ROM_BASE       0x60000000
+#define __ROM_SIZE       0x00200000
+
+#define __RAM_BASE       0x60200000
+#define __RAM_SIZE       0x00200000
+
+#define __RW_DATA_SIZE   0x00100000
+#define __ZI_DATA_SIZE   0x000F0000
+
+#define __STACK_SIZE     0x00001000
+#define __HEAP_SIZE      0x00008000
+
+#define __UND_STACK_SIZE 0x00000100
+#define __ABT_STACK_SIZE 0x00000100
+#define __SVC_STACK_SIZE 0x00000100
+#define __IRQ_STACK_SIZE 0x00000100
+#define __FIQ_STACK_SIZE 0x00000100
+
+#define __TTB_BASE       0x60500000
+#define __TTB_SIZE       0x00004000
+
+#endif /* __MEM_ARMCA9_H */

CMSIS/CoreValidation/Layer/Target/CA9QEMU/Include/ARMCA9.h

@@ -0,0 +1,96 @@
+/**************************************************************************//**
+ * @file     ARMCA9.h
+ * @brief    CMSIS-Core(A) device header for QEMU vexpress-a9
+ ******************************************************************************
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/* Copyright (c) 2026 Arm Limited. All rights reserved. */
+
+#ifndef ARMCA9_H
+#define ARMCA9_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+typedef enum IRQn
+{
+  SGI0_IRQn            =  0,
+  SGI1_IRQn            =  1,
+  SGI2_IRQn            =  2,
+  SGI3_IRQn            =  3,
+  SGI4_IRQn            =  4,
+  SGI5_IRQn            =  5,
+  SGI6_IRQn            =  6,
+  SGI7_IRQn            =  7,
+  SGI8_IRQn            =  8,
+  SGI9_IRQn            =  9,
+  SGI10_IRQn           = 10,
+  SGI11_IRQn           = 11,
+  SGI12_IRQn           = 12,
+  SGI13_IRQn           = 13,
+  SGI14_IRQn           = 14,
+  SGI15_IRQn           = 15,
+
+  GlobalTimer_IRQn     = 27,
+  PrivTimer_IRQn       = 29,
+  PrivWatchdog_IRQn    = 30,
+
+  Watchdog_IRQn        = 32,
+  Timer0_IRQn          = 34,
+  Timer1_IRQn          = 35,
+  RTClock_IRQn         = 36,
+  UART0_IRQn           = 37,
+  UART1_IRQn           = 38,
+  UART2_IRQn           = 39,
+  UART3_IRQn           = 40,
+  MCI0_IRQn            = 41,
+  MCI1_IRQn            = 42,
+  AACI_IRQn            = 43,
+  Keyboard_IRQn        = 44,
+  Mouse_IRQn           = 45,
+  CLCD_IRQn            = 46,
+  Ethernet_IRQn        = 47,
+  VFS2_IRQn            = 73,
+} IRQn_Type;
+
+/* QEMU vexpress-a9 private peripheral region. */
+#define VEXPRESS_A9_PRIVATE_BASE              (0x1E000000UL)
+#define GIC_DISTRIBUTOR_BASE                  (VEXPRESS_A9_PRIVATE_BASE + 0x00001000UL)
+#define GIC_INTERFACE_BASE                    (VEXPRESS_A9_PRIVATE_BASE + 0x00000100UL)
+#define TIMER_BASE                            (VEXPRESS_A9_PRIVATE_BASE + 0x00000600UL)
+#define L2C_310_BASE                          (VEXPRESS_A9_PRIVATE_BASE + 0x0000A000UL)
+
+#if   defined (__CC_ARM)
+  #pragma push
+  #pragma anon_unions
+#elif defined (__ICCARM__)
+  #pragma language=extended
+#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+  #pragma clang diagnostic push
+  #pragma clang diagnostic ignored "-Wc11-extensions"
+  #pragma clang diagnostic ignored "-Wreserved-id-macro"
+#endif
+
+#define __CA_REV                  0x0000U
+#define __CORTEX_A                9U
+#define __FPU_PRESENT             1U
+#define __GIC_PRESENT             1U
+#define __TIM_PRESENT             1U
+#define __L2C_PRESENT             0U
+
+#include "core_ca.h"
+#include <system_ARMCA9.h>
+
+#if   defined (__CC_ARM)
+  #pragma pop
+#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+  #pragma clang diagnostic pop
+#endif
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* ARMCA9_H */

CMSIS/CoreValidation/Layer/Target/CA9QEMU/Source/mmu_ARMCA9.c

@@ -0,0 +1,55 @@
+/**************************************************************************//**
+ * @file     mmu_ARMCA9.c
+ * @brief    MMU configuration for QEMU vexpress-a9
+ ******************************************************************************
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/* Copyright (c) 2026 Arm Limited. All rights reserved. */
+
+#include "ARMCA9.h"
+#include "mem_ARMCA9.h"
+
+#define TTB_BASE ((uint32_t *)__TTB_BASE)
+#define VEXPRESS_A9_RAM_BASE (0x60000000U)
+#define VEXPRESS_A9_RAM_SIZE (0x08000000U)
+
+static uint32_t Sect_Normal_Cod;
+static uint32_t Sect_Normal_RW;
+static uint32_t Sect_Device_RO;
+static uint32_t Sect_Device_RW;
+
+void MMU_CreateTranslationTable(void)
+{
+    mmu_region_attributes_Type region;
+
+    /* Start with a faulting 4 GB address space. */
+    MMU_TTSection(TTB_BASE, 0U, 4096U, DESCRIPTOR_FAULT);
+
+    section_normal_cod(Sect_Normal_Cod, region);
+    section_normal_rw(Sect_Normal_RW, region);
+    section_device_ro(Sect_Device_RO, region);
+    section_device_rw(Sect_Device_RW, region);
+
+    /*
+     * Identity-map all high memory. QEMU's semihosting SYS_HEAPINFO places
+     * the C library stack near the top of this 128 MiB region.
+     */
+    MMU_TTSection(TTB_BASE, VEXPRESS_A9_RAM_BASE,
+                  VEXPRESS_A9_RAM_SIZE / 0x100000U, Sect_Normal_RW);
+
+    /* Override the linked code region with read-only executable attributes. */
+    MMU_TTSection(TTB_BASE, __ROM_BASE, __ROM_SIZE / 0x100000U, Sect_Normal_Cod);
+
+    /* QEMU aliases its first 64 MiB flash bank at address zero. */
+    MMU_TTSection(TTB_BASE, 0x00000000U, 64U, Sect_Device_RO);
+
+    /* QEMU vexpress-a9 motherboard and Cortex-A9 private peripherals. */
+    MMU_TTSection(TTB_BASE, 0x10000000U, 1U, Sect_Device_RW);
+    MMU_TTSection(TTB_BASE, VEXPRESS_A9_PRIVATE_BASE, 1U, Sect_Device_RW);
+
+    __set_TTBR0(__TTB_BASE | 0x48U);
+    __ISB();
+    __set_DACR(1U);
+    __ISB();
+}

CMSIS/CoreValidation/Layer/Target/CA9QEMU/Target.clayer.yml

@@ -0,0 +1,39 @@
+layer:
+  type: Target
+  description: Cortex-A9 target for QEMU vexpress-a9
+
+  components:
+    - component: ARM::CMSIS:CORE
+    - component: Device:IRQ Controller:GIC
+
+  add-path:
+    - ./Config
+    - ./Include
+    - ../CA9/RTE/Device/ARMCA9
+
+  # QEMU TCG does not model dirty cache-line data that can be discarded.
+  define:
+    - TC_CAL1CACHE_INVALIDATEDCACHEALL: 0
+
+  linker:
+    - script: ../CA9/RTE/Device/ARMCA9/ARMCA9_ac6.sct
+      for-compiler:
+        - AC6
+    - script: ../CA9/RTE/Device/ARMCA9/ARMCA9_gcc.ld
+      for-compiler:
+        - GCC
+    - script: ../CA9/RTE/Device/ARMCA9/ARMCA9_clang.ld
+      for-compiler:
+        - CLANG
+    - regions: Config/mem_ARMCA9.h
+      for-compiler:
+        - AC6
+        - GCC
+        - CLANG
+
+  groups:
+    - group: QEMU vexpress-a9 Startup
+      files:
+        - file: ../CA9/RTE/Device/ARMCA9/startup_ARMCA9.c
+        - file: ../CA9/RTE/Device/ARMCA9/system_ARMCA9.c
+        - file: ./Source/mmu_ARMCA9.c

CMSIS/CoreValidation/Project/Validation.csolution.yml

@@ -127,6 +127,10 @@ solution:
     - type: CA9
       device: ARMCA9
 
+    #Target: CA9 on QEMU vexpress-a9
+    - type: CA9QEMU
+      device: ARMCA9
+
   build-types:
     - type: none
       optimize: none

CMSIS/CoreValidation/Project/Validation/Validation.cproject.yml

@@ -33,6 +33,7 @@ project:
         - +CA5
         - +CA7
         - +CA9
+        - +CA9QEMU
 
     #Target: CM0
     - layer: ../../Layer/Target/CM0/Target.clayer.yml
@@ -163,3 +164,8 @@ project:
     - layer: ../../Layer/Target/CA9/Target.clayer.yml
       for-context:
         - +CA9
+
+    #Target: CA9 on QEMU vexpress-a9
+    - layer: ../../Layer/Target/CA9QEMU/Target.clayer.yml
+      for-context:
+        - +CA9QEMU