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🔭 I’m currently working on developing a superscalar version of the Core-V Wally Processor
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🌱 I’m currently learning Computer Systems
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💬 Ask me about designing performant computational accelerators, such as this FPGA-Based Edge Detection
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📫 How to reach me vkrishna@hmc.edu
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cvw
cvw PublicForked from openhwfoundation/cvw
CORE-V Wally is a configurable RISC-V Processor associated with RISC-V System-on-Chip Design textbook. Contains a 5-stage pipeline, support for A, B, C, D, F, M and Q extensions, and optional cache…
SystemVerilog 1
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cvw-arch-verif
cvw-arch-verif PublicForked from openhwfoundation/cvw-arch-verif
The purpose of the repo is to support CORE-V Wally architectural verification
SystemVerilog 1
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troyrkaufman/e155_edge_detection_hardware_accelerator
troyrkaufman/e155_edge_detection_hardware_accelerator PublicA complex MCU and FPGA design will apply an edge detection filter to an image supplied by a OV2640 camera module
C
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