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1. MIPS-ISA MIPS-ISA Public

   The MIPS ISA (Instruction Set Architecture) is a 32-bit RISC (Reduced Instruction Set Computer) architecture known for its simplicity and efficiency.

   C 1

2. Power-Reduction-in-Half-Subtractor-by-Gate-Sizing-Techniques Power-Reduction-in-Half-Subtractor-by-Gate-Sizing-Techniques Public

   Performed power analysis of a half subtractor circuit using parametric analysis for 180nm technology with Cadence Virtuoso

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3. Synthesizable-Parametrized-ALU-Design Synthesizable-Parametrized-ALU-Design Public

   Arithmetic and logical units are an integral part of any SOC that performs Arithmetic and logical operations. The ALU designed in this project supports variety of functions including arithmetic ope…

   Verilog 1

4. Universal-Shift-Register-and-Johnson-Counter Universal-Shift-Register-and-Johnson-Counter Public

   The register and counter circuit are simulated and designed using four 4:1 MUX which is used to select the operations (like SISO, PISO, PIPO, SIPO), IC555 timer is used to give clock pulse and D fl…

   1

5. Verilog-Based-Verification-of-a-MOD-10-Counter-Design Verilog-Based-Verification-of-a-MOD-10-Counter-Design Public

   The MOD-10 counter was functionally verified using a Verilog testbench to validate reset, load, increment, and rollover operations. Out of 2987 executed test cases, 2937 passed successfully, achiev…

   Verilog 1