AtlasRV: A 5-Stage Pipelined RV32I Processor ASIC

Status: Version 1 complete; Version 2 stabilized and tagged v2_pipeline_stabilized; Version 2.5 verification and RTL quality upgrade is next.

AtlasRV is a SystemVerilog project building a 32-bit RV32I processor toward an eventual ASIC implementation flow. It prioritizes correctness, verification quality, measurable RTL quality, and disciplined documentation before synthesis, STA, and physical implementation.

Project Overview

AtlasRV implements a classic single-issue, in-order 5-stage pipeline:

IF  - Instruction Fetch
ID  - Instruction Decode / Register Read
EX  - Execute / Branch Resolution
MEM - Data Memory Access
WB  - Register Writeback

Version 1 provides the completed single-cycle reference core. Version 2 provides the stabilized pipeline baseline. Version 2.5 focuses on reproducible regression, lint closure, independent references, assertions, coverage, CI smoke tests, and documentation without adding ISA or microarchitecture features.

Current Status

• 5-stage IF/ID/EX/MEM/WB pipeline
• EX/MEM and MEM/WB forwarding, including dual-source cases
• WB-to-ID register-file bypass
• Load-use hazard detection with a one-cycle stall, pipeline hold, and bubble insertion
• Branch, JAL, and JALR resolution in EX with wrong-path flush
• Byte, halfword, and word loads and stores, with signed and unsigned loads
• Directed pipeline regression
• An initial constrained-random differential smoke regression against the single-cycle reference core
• Documented fixes, including the permanent BUG-001 same-register source/destination regression in the bug log

The 10-seed differential result is an initial smoke test, not comprehensive verification. Independent-model comparison, Spike comparison, assertions, broader coverage, and CI are Version 2.5 work.

Architecture and ISA Scope

AtlasRV targets a single-issue, in-order RV32I processor with separate instruction and data memory interfaces. The implemented instruction scope includes RV32I R-type and I-type ALU instructions, loads, stores, conditional branches, JAL, JALR, LUI, and AUIPC. See the project specification for the instruction list.

CSR instructions, privilege modes, exceptions, interrupts, branch prediction, caches, MMU support, Linux, and complex SoC buses are outside the current scope.

Implemented Modules

Key RTL includes:

• rtl/rv32i_pipeline_core.sv - Integrated 5-stage pipeline core
• rtl/rv32i_pkg.sv - RV32I package definitions and control structures
• rtl/alu.sv - Arithmetic, logic, comparison, and shift operations
• rtl/regfile.sv - 32-entry pipeline register file with x0 handling and WB-to-ID bypass
• rtl/imm_gen.sv - RV32I immediate generation
• rtl/decoder.sv - Instruction decode and control generation
• rtl/branch_unit.sv - Branch comparison and decision logic
• rtl/load_store_unit.sv - Byte enables, store alignment, and load extension
• rtl/forwarding_unit.sv - EX/MEM and MEM/WB forwarding selection
• rtl/hazard_detection_unit.sv - Load-use hazard detection
• Pipeline stage and stage-register modules under rtl/
• rtl_single_cycle/rv32i_single_cycle_core.sv - Completed single-cycle reference core
• rtl_single_cycle/regfile_v1.sv - Bypass-free register file required by the single-cycle core

Verification Status

Directed testbenches under tb/ cover the ALU, register file, immediate generator, decoder, branch unit, load/store unit, memory models, single-cycle core, and pipeline core. Pipeline regression covers forwarding, load-use stalls, WB-to-ID bypass, control-flow flush, ALU edge cases, LUI/AUIPC, byte/halfword memory operations, and BUG-001 regressions. The initial constrained-random differential smoke regression compares final register state between Version 2 and Version 1 across 10 runs.

Version 1 and Version 2 share several RTL leaf modules, so their agreement demonstrates equivalence rather than independent ISA correctness. Version 2.5 adds an independent architectural model, Spike comparison, and selected architectural tests to address that limitation. See the verification plan.

Roadmap

Version	Description	Status
Version 0	Project scaffolding, RV32I leaf modules, directed module tests	Complete
Version 1	Single-cycle RV32I reference core	Complete
Version 2	5-stage RV32I pipeline (stabilized)	Complete and tagged (v2_pipeline_stabilized)
Version 2.5	Verification and RTL Quality Upgrade	Next
Version 3	Lightweight Professional Verification Environment	Planned
Version 4	ASIC Front-End Signoff	Planned
Version 5	Synthesis and Static Timing Analysis	Planned
Version 6	Functional Gate-Level Simulation	Planned
Version 7	OpenLane Physical Implementation	Planned
Version 8	Final Portfolio and Release Package	Planned

See the project roadmap for the Version 2.5 execution sequence, deliverables, and exit criteria.

Repository Structure

.
|-- docs/              Specification, roadmap, verification, and engineering notes
|-- rtl/               5-stage pipeline core, stages, registers, and shared RV32I RTL
|-- rtl_single_cycle/  Completed Version 1 single-cycle reference core
|-- tb/                Directed and constrained-random SystemVerilog testbenches
|-- waveforms/         Local generated simulation artifacts
|-- Makefile           Current simulation entry points

Future phases will add automation, reports, assertions, coverage, CI, synthesis, STA, gate-level simulation, and physical-design artifacts. Generated outputs should remain excluded from version control.

Tools

• SystemVerilog
• Icarus Verilog / vvp
• GTKWave
• Git / GitHub

Version 2.5 plans to add Verilator lint, independent-reference tooling, selected RISC-V architectural tests, and a small GitHub Actions smoke workflow.

Learning and Engineering Focus

AtlasRV is a hands-on processor and ASIC engineering project. Its focus is disciplined RTL design, RV32I datapath and control, pipeline hazards, reproducible verification, measurable quality, synthesis readiness, timing awareness, and a realistic ASIC implementation path without overstating the current level of completion.