GitHub - C-Dharshan/UART: Universal Asynchronous Receiver Transmitter implementation using Verilog HDL · GitHub

Name		Name	Last commit message	Last commit date
UART protocol.cache		UART protocol.cache
UART protocol.hw		UART protocol.hw
UART protocol.ip_user_files		UART protocol.ip_user_files
UART protocol.sim/sim_1/behav/xsim		UART protocol.sim/sim_1/behav/xsim
UART protocol.srcs		UART protocol.srcs
UART Tx architecture.pdf		UART Tx architecture.pdf
UART protocol.xpr		UART protocol.xpr

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Universal Asynchronous Receiver Transmitter implementation using Verilog HDL

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