Yarc

Yet Another RiscV Core, implements RV32I

Yarc Platform Architecture

Core Microarchitecture

The core follows the standard 5-stage pipelined model.

Memory Subsystem

Instruction Cache

Data Cache

Video Core

Supported Extensions and Features

• Zicsr
• M(multiplication/division)
• Atomics
• Debug Module
• S mode and MMU

Milestones on the way to Boot Linux

• rv32ui tests ok
• rv32mi tests ok
• rv32um tests ok
• rv32ua tests ok
• Implement M extension
• Implement A extension
• Attempt to boot OpenSBI

FPGA Synthesis

TODO