4bit-processor-verilog

Overview

This repository contains the complete design and simulation of a 4-bit processor implemented using Verilog HDL. The processor is modeled at the RTL level and verified through simulation in ModelSim, demonstrating fundamental concepts of processor architecture and digital system design.

Processor Description

The processor follows a simple fetch–decode–execute architecture. It consists of a 4-bit program counter, a small instruction memory, and a register file with four 4-bit general-purpose registers. The design supports basic arithmetic, logic, load, and control instructions. Internal registers are exposed as outputs to simplify waveform observation and debugging during simulation.

Features

• 4-bit data path architecture

• Program Counter for sequential instruction execution

• 16 × 8-bit Instruction Memory

• Register File with four 4-bit registers

Supported instructions:

• LOAD

• ADD

• SUB

• AND

• OR

• HALT

• Fetch–Decode–Execute operation cycle

Instruction Format

Each instruction is 8 bits wide.

Bits Description

• [7:4] Opcode
• [3:2] Destination Register (rd)
• [1:0] Source Register / Immediate (rs)

Repository Structure

• RTL_code (Processor RTL design)
• test_bench (Testbench for simulation)
• waveform (Simulation result)
• README.md (Project documentation)

Learning Outcomes

• Understanding basic processor architecture

• Hands-on experience with Verilog HDL

• Instruction decoding and execution logic

• Register file and program counter design

• RTL simulation and waveform analysis in ModelSim

Tools Used

• Verilog HDL – Hardware description language

• ModelSim – Simulation and waveform analysis

Author

CHARUNIVETHITHA S