http://ei2030.github.io/FemtoTX
Several pull requests have been merged srvedulageth/solar_femtoTx#4
Vedula got DDR3 pings completed! Zero packet loss & 100% pings worked!
Vedula says, "I am able to get simulation working with DRAM and testing on emulation."
Vedula has designed a bridge to connect Wishbone and Application interface.
Vedula has reported pings work, while timeouts occur. As of 12-3, he is currently debugging.
Vedula has completed TX and RX continuous testing!
9ab9ae3b-c004-4fb8-89ea-1b8fd92fd37d.mp4
Next up: validation on FPGA of full duplex.
Vedula has completed EthMac Tx. He sent data from the ZAP SoC to his Windows desktop and captured the Tx using Wireshark. He will test Rx now and then work on booting linux.
VS reports:
- Checked in code with EthMAC integrated.
- Implemented SoC with Ethmac. No errors and able to transfer on uart.
- Next Task Write Driver for EthMAC.
the ZAP core has cache:
https://en.wikipedia.org/wiki/Transistor_count#Microprocessors
https://www.techrxiv.org/users/814616/articles/1270555-a-heuristic-method-for-designing-solar-circuits Estimating the power consumption can be tricky. At 130nm, 22nm, and 3nm. The budget of this project will allow 130nm, but it's unclear how much funding would be needed for 22nm, and eDRAM
https://www.musesemi.com/full-block-tapeout-pricing https://www.cmc.ca/globalfoundries-22fdx-fdsoi-22-nm/ https://www.src.org/calendar/e003676/barth.pdf
Vedula has completed synthesis and loading of the FPGA with UART & ZAP Core. He made an LED test, which shows 3 continuously lit LEDs, and one blinking. He connected UART Tx (output from ZAP SoC), and whenever he presses a key, the LED comes back as it was connected to tx_0, which is the blinking LED.
46795Edc-A1a3-426F-9B72-F7034126d822.mp4
This step was an intermediate stage before he can begin booting linux, which he will work on next.
https://www.allaboutcircuits.com/ip-cores/all/P720/ Other ISAs that may be of use/complement ZAP core
https://github.com/stnolting/neorv32
https://www.allaboutcircuits.com/ip-cores/processor/
https://www.allaboutcircuits.com/ip-cores/processor/arm4u/ https://github.com/freecores/arm4u
https://www.allaboutcircuits.com/ip-cores/processor/aor3000/ https://github.com/alfikpl/aoR3000
https://www.allaboutcircuits.com/ip-cores/processor/mips-enhanced/
https://opencores.org/projects/mips789
https://github.com/freecores/mips789/tree/master/core
See paper for background and candidate cores.
FA526: https://www.innopower-tech.com/html/products/functional/FA5.jsp
Current Milestone 3: Simulating Linux
Vedula is working on implementing the ZAP SoC on the FPGA Arty xc7a100tcsg324. A Storm Core (ARM7) has been found to be completely implemented in an FPGA w/ Altera, therefore we may switch to that core, add EthMac, and implement that one instead.
Vedula says:
- I just created a tag, solar_femtoTX_Milestone-1
A very very basic EthMAC access test i put in.
- SoC has ZAP core + EthMAC + UART(2 Instances) + Timer(2 Instances) + VIC(1 Instance)
- Synthesized SoC for Xilinx xc7a100tcsg324-1.
- Test bench is up with these modules. Ran few tests.
Synthesis performed on an ARTY A7 (Artix-A7) 100T
The Ethernet controller will be using the EthMac core
The FemtoTX will be similar the ARM926EJ-based SAM9x60 and NU980 boards by Microchip and Nuvoton
https://github.com/EI2030/Low-power-E-Paper-OS/blob/master/Hyperlinks.md#arm9-armv5-socs
Vedula has completed synthesis of a ZAP processor on an Artix A7!:
Vedula's notes:
"Please see Save/ dir for Synthesis report.
Added a separate Readme for convenience."
https://github.com/srvedulageth/solar_femtoTx/blob/main/README.solar_femtoTx