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1. -21days0fverilog -21days0fverilog Public

   100 days of RTL coding

   SystemVerilog

2. AXI3-Memory AXI3-Memory Public

   AXI3 Memory is the Slave module which consists of all 5 Channels of AXI Protocol. This module is designed in Verilog HDL and Synthesized in Vivado Tool.

3. multiply_fp32 multiply_fp32 Public

   Forked from phinitylabs/multiply_fp32

   FP32 Multiplier - Verilog agent eval problem

   SystemVerilog