data(cpu): fill process node and L3 cache for 310 Pentium/Celeron CPUs

[Seungpyo1007]

What

310 records gain 500 previously-null fields — process_node 287, l3_cache_mb 213 — from the Wikipedia Intel Celeron and Pentium list pages.

Running total with #132 and #133: CPU process_node coverage 24% → 53%, l3_cache_mb 19% → 53%.

Parser change this batch needed

The Xeon pages (#133) each covered a single microarchitecture, so the node could be taken from the page. Celeron and Pentium pages mix generations — one page spans Covington (250 nm) through modern parts — so that shortcut would have been wrong.

The parser now resolves the node from the enclosing section heading:

=== "Coppermine-128" (180 nm) ===
=== "Prescott-256" (90 nm) ===

and leaves the field empty when a heading carries no node, rather than inheriting the previous section's value. Verified across the historical range: Celeron 266 → 250 nm (Covington), Celeron 420 → 65 nm (Conroe-L). The Xeon results were re-checked after the change and are unchanged (Skylake page still 151 rows, all 14 nm).

Correctness

• Same confirm-before-write rule: core count must match exactly and TDP within 1 W when both sides have it. 1 of 319 matches was dropped.
• Applied values sit in the expected ranges — nodes 65/45/32/22/14/10 nm, L3 1–6 MB (Celeron/Pentium parts have small caches).
• Source URLs were HTTP-verified before writing. One generated link returned 404 (..._Pentium_Dual_Core_..., the real title is hyphenated); it was resolved through the API to the canonical page rather than left broken in the data.

Only empty fields are written, nothing existing is overwritten, verified untouched.

python -m app.validate → Data validation passed. Dump refreshed for the 310 changed pages only.

Closes #1

[TechEngineBot]

🔎 Data verification — Tier 0 (offline existence/trust)

Scored by app.verify; posted by TechEngineBot. Informational only — the structural gate (app.validate) is separate and authoritative for merge.

Changed records in this PR

850 record(s) scored.

%%{init: {"theme":"base","themeVariables":{"pie1":"#3fb950","pie2":"#d29922","pie3":"#f85149","pieStrokeWidth":"0px","pieOpacity":"1"}}}%%
pie showData
    title Verification bands — all records
    "Green" : 310
    "Yellow" : 540
    "Red" : 0

Loading

Category	Distribution	Total	🟢	🟡	🔴	🟢 %
cpu	🟩🟩🟩🟩🟨🟨🟨🟨🟨🟨🟨🟨	850	310	540	0	36.5%
All	🟩🟩🟩🟩🟨🟨🟨🟨🟨🟨🟨🟨	850	310	540	0	36.5%

Full-dataset baseline

105742 record(s) scored.

%%{init: {"theme":"base","themeVariables":{"pie1":"#3fb950","pie2":"#d29922","pie3":"#f85149","pieStrokeWidth":"0px","pieOpacity":"1"}}}%%
pie showData
    title Verification bands — all records
    "Green" : 14083
    "Yellow" : 89747
    "Red" : 1912

Loading

Category	Distribution	Total	🟢	🟡	🔴	🟢 %
brand	🟩🟨🟨🟨🟨🟨🟨🟨🟨🟨🟨🟨	207	24	183	0	11.6%
soc	🟩🟨🟨🟨🟨🟥🟥🟥🟥🟥🟥🟥	2104	123	680	1301	5.8%
smartphone	🟩🟨🟨🟨🟨🟨🟨🟨🟨🟨🟨🟥	93396	11602	81206	588	12.4%
tablet	🟩🟨🟨🟨🟨🟨🟨🟨🟨🟨🟨🟥	3455	174	3266	15	5.0%
watch	🟩🟨🟨🟨🟨🟨🟨🟨🟨🟨🟨🟥	433	11	415	7	2.5%
pda	🟩🟩🟨🟨🟨🟨🟨🟨🟨🟨🟨🟥	140	27	112	1	19.3%
gpu	🟩🟨🟨🟨🟨🟨🟨🟨🟨🟨🟨🟨	2030	245	1785	0	12.1%
cpu	🟩🟩🟩🟩🟩🟩🟨🟨🟨🟨🟨🟨	3977	1877	2100	0	47.2%
All	🟩🟩🟨🟨🟨🟨🟨🟨🟨🟨🟨🟥	105742	14083	89747	1912	13.3%

_{green = authoritative source + complete + consistent · yellow = plausible, needs confirmation · red = sparse/weak source or a hard contradiction. Promotion to verified runs in the scheduled verify-network workflow.}

[TechEngineBot]

TechEngine change review: PASS

• PR: data(cpu): fill process node and L3 cache for 310 Pentium/Celeron CPUs #134
• Ref: data/cpu-pentium-celeron-specs
• Commit: e819c4e
• Requested by: @Seungpyo1007
• Run: https://github.com/GetTechAPI/TechEngine/actions/runs/30429426359

Check	Result
python -m app.validate	PASS
python integrity_check.py TechAPI/data --strict	PASS

Changed data

Category	Added	Modified	Deleted	Added verified	Added unverified	Added Kaggle-sourced
brand	0	0	0	0	0	0
soc	0	0	0	0	0	0
smartphone	0	0	0	0	0	0
tablet	0	0	0	0	0	0
watch	0	0	0	0	0	0
pda	0	0	0	0	0	0
gpu	0	0	0	0	0	0
cpu	0	540	0	0	0	0

Changed record examples

cpu modified

• cpu/intel/2009/enterprise/intel-xeon-e5502.json - Intel Xeon E5502
• cpu/intel/2009/enterprise/intel-xeon-e5504.json - Intel Xeon E5504
• cpu/intel/2009/enterprise/intel-xeon-e5506.json - Intel Xeon E5506
• cpu/intel/2009/enterprise/intel-xeon-w3503.json - Intel Xeon W3503
• cpu/intel/2009/enterprise/intel-xeon-w3505.json - Intel Xeon W3505
• cpu/intel/2010/enterprise/intel-xeon-e5503.json - Intel Xeon E5503
• cpu/intel/2010/enterprise/intel-xeon-e5507.json - Intel Xeon E5507
• cpu/intel/2010/enterprise/intel-xeon-e5620.json - Intel Xeon E5620
• cpu/intel/2010/enterprise/intel-xeon-e5630.json - Intel Xeon E5630
• cpu/intel/2010/enterprise/intel-xeon-e5640.json - Intel Xeon E5640
• cpu/intel/2010/enterprise/intel-xeon-l5609.json - Intel Xeon L5609
• cpu/intel/2010/enterprise/intel-xeon-l5630.json - Intel Xeon L5630
• cpu/intel/2010/enterprise/intel-xeon-l5640.json - Intel Xeon L5640
• cpu/intel/2010/enterprise/intel-xeon-w3680.json - Intel Xeon W3680
• cpu/intel/2010/enterprise/intel-xeon-x5650.json - Intel Xeon X5650
• ... 525 more

Heuristic review

• Heuristic warnings: none found.

[TechEngineBot]

TechEngine validation stats: PASS

• PR: data(cpu): fill process node and L3 cache for 310 Pentium/Celeron CPUs #134
• Ref: data/cpu-pentium-celeron-specs
• Commit: e819c4e
• Run: https://github.com/GetTechAPI/TechEngine/actions/runs/30429426359

Data summary

Category	Total	Verified	Unverified	Missing verified	Tracked	Verified % of tracked
brand	207	10	197	0	207	4.8%
soc	2104	123	1981	0	2104	5.8%
smartphone	93396	8453	84943	0	93396	9.1%
tablet	3455	174	3281	0	3455	5.0%
watch	433	11	422	0	433	2.5%
pda	140	27	113	0	140	19.3%
gpu	2030	244	1786	0	2030	12.0%
cpu	3977	986	2991	0	3977	24.8%
all	105742	10028	95714	0	105742	9.5%

Warning

Tracked verified coverage is below 50% for watch 2.5% (11/433), brand 4.8% (10/207), tablet 5.0% (174/3455), soc 5.8% (123/2104), smartphone 9.1% (8453/93396), all 9.5% (10028/105742), gpu 12.0% (244/2030), pda 19.3% (27/140), and 1 more.
Tracked coverage excludes records missing the verified field; see the Missing verified column for those records.
This does not fail validation. Keep imported records verified: false until manual audit, but treat this as follow-up verification work before relying on the affected categories as curated data.

Validation notes

• Full advisory outlier listings are suppressed on successful runs because they are dataset-wide and mostly stable between PRs.
• Failure runs still include a detailed log excerpt for debugging.

Key output:

## app.validate
## integrity_check.py --strict
loaded CPU=3977 GPU=2030
✅ integrity gate: no hard anomalies.

Integrity section	Flagged lines
structural	0
CPU name/tier consistency (desktop mainstream only)	0
CPU single>multi (cinebench/geekbench — should be multi>=single)	0
CPU era-vs-score outliers	8
CPU cross-source ratio outliers (possible wrong-variant)	152
GPU cross-source ratio outliers + sanity	18