🔌 ADLD: Advanced Digital Logic & State Machine Simulator

Synchronous Finite State Machines (FSM), Logic Gate Emulation & Truth Table Verification

An interactive digital circuit and sequential state machine simulator verifying flip-flop state transitions, propagation delays, and Boolean logic reduction.

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⚡ The Architectural Vision

Visualizing synchronous sequential logic, propagation delays, and edge-triggered state transitions during hardware design is essential for computer architecture education.

ADLD provides an empirical simulation environment for digital systems:

• Sequential State Machine Modeling: Mealy and Moore Finite State Machine (FSM) state transition analysis.
• Synchronous Flip-Flops: D, T, and JK flip-flop excitation table validation.
• Combinational Optimization: Karnaugh Map (K-Map) minimization and Boolean reduction proofs.

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🏗️ State Machine Architecture

stateDiagram-v2
    [*] --> ResetState: System Reset Active
    ResetState --> S0: Clock Edge (CLK)
    S0 --> S1: Input X = 1
    S0 --> S0: Input X = 0
    S1 --> S2: Input X = 1
    S1 --> S0: Input X = 0
    S2 --> S0: Sequence Detected (Z = 1)

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🧩 Antigravity Skills & Tooling

• clean-code: Modular separation between combinational gate logic and sequential clock registers.
• diagram-design: State transition diagrams and gate-level circuit schematics.

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📄 License

Distributed under the MIT License. Maintained by Jaswanth Reddy — Passionate learner & creative problem solver learning from and giving back to the open-source community.