EE @ UWaterloo · firmware + RTL · i design hardware and write firmware. i've shipped FreeRTOS drivers, built a RISC-V CPU from scratch, and taped out a systolic array on an FPGA. currently searching for hardware/firmware co-ops where i can touch silicon.
| languages | C C++ Python Verilog SystemVerilog RISC-V asm |
| firmware | FreeRTOS ESP32 STM32 ARM Cortex-M DMA bare-metal |
| protocols | AXI4-Lite Wishbone SPI I2C UART BLE MQTT |
| RTL / tools | Vivado Gowin EDA cocotb ModelSim KiCad GDB/JTAG |
| project | what it is |
|---|---|
systolic-array-accelerator |
8x8 MNIST inference accelerator on FPGA. INT8 quantised. 148 MHz Fmax. it actually works. |
axi4-lite-subsystem |
parametric AXI4-Lite slave register file in SystemVerilog. all 5 channels, WSTRB, SLVERR. GPIO peripheral wired up. cocotb testbench included. |
riscv-soc |
RV32I 5-stage pipeline CPU on FPGA with full bare-metal toolchain. built from scratch. both the CPU and the regret. |
stm32-oscilloscope |
bare-metal DMA-driven ADC on Cortex-M4. 1 MSps. sub-ms capture latency. streams to Python visualiser. |
- RTL @ UWASIC (BVH traversal pipeline, AXI4-Lite peripheral subsystem, SPI/PWM peripherals)
- embedded @ WARG (STM32 safety state machines, GPS, magnetometer drivers)
- 1B term @ UWaterloo · open to Fall 2026 co-op conversations
linkedin · jwongkar@uwaterloo.ca · waterloo, on