16-bit Processor — Verilog

A fully functional 16-bit processor implemented in Verilog, featuring a custom ISA with a register file, ALU, bus multiplexer, and FSM-based control unit. Simulated in ModelSim and synthesized in Intel Quartus Prime.

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Overview

The processor operates on 16-bit data loaded through a DIN input. Instructions are 9-bit encoded and executed over up to 4 clock cycles using a 2-bit time-step counter (T0–T3). Execution begins when run is asserted and signals completion via a done pulse.

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Tools

• Language: Verilog
• Simulation: ModelSim
• Synthesis: Intel Quartus Prime

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ISA — Supported Instructions

Instruction	Operation	Clock Cycles
mv Rx, Ry	Rx ← Ry	2
mvi Rx, #D	Rx ← D (immediate)	2
add Rx, Ry	Rx ← Rx + Ry	4
sub Rx, Ry	Rx ← Rx − Ry	4

Instruction encoding: 9-bit format III XXX YYY

• III — opcode
• XXX — destination register (Rx)
• YYY — source register (Ry)

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Architecture

Modules

reg_file8 — Register File

• 8 general-purpose 16-bit registers (R0–R7)
• Per-register write enable (we[7:0])
• Asynchronous reset

alu_addsub — ALU

• Combinational add/subtract unit
• sub=0 → addition, sub=1 → subtraction
• Operates on register A (first operand) and the Bus (second operand)

bus_mux — Bus Multiplexer

• 16-bit wide, 10-input mux
• Sources: R0–R7 (sel 0–7), DIN (sel 8), G register (sel 9)
• Drives the shared data Bus

control_unit — FSM Control Unit

• 2-bit time-step counter T (T0–T3)
• Generates all control signals: ir_load, a_load, g_load, r_we, bus_sel, alu_sub
• done asserted as a 1-cycle pulse at instruction completion

proc_top — Top Level

• Instantiates and wires all submodules
• Contains internal registers: IR (instruction), A (ALU operand), G (ALU result)

Execution Flow

Short instructions (mv, mvi) — 2 cycles:

• T0 — Fetch: load IR from DIN
• T1 — Execute: route source to Bus, write to Rx, assert Done

Long instructions (add, sub) — 4 cycles:

• T0 — Fetch: load IR from DIN
• T1 — Load A: route Rx to Bus, latch into register A
• T2 — Compute: route Ry to Bus, ALU computes A ± Ry, latch result into G
• T3 — Writeback: route G to Bus, write to Rx, assert Done

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Testbench

The testbench validates all instruction types:

1. MVI R0, 4 — load immediate value 4 into R0
2. MVI R1, 3 — load immediate value 3 into R1
3. ADD R0, R1 — R0 ← R0 + R1
4. Asserts R0 == 7 and prints PASS/FAIL