DMA Controller — VHDL

A DMA controller implemented in VHDL, capable of offloading data transfers between two memory banks without CPU intervention.

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Overview

The controller accepts a source address, destination address, and word count — then transfers 16-bit words from source memory to destination memory using a 4-step FSM, asserting a DONE flag upon completion.

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Tools

• Language: VHDL
• Simulation: ModelSim
• Synthesis: Intel Quartus Prime

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Architecture

The design is split into two levels:

Logic Level (dma_logic) — contains all FSM and datapath logic:

• Manages source/destination address pointers and word counter
• Executes a fixed 4-step read/write sequence per word:
  • STEP 0 — Assert source read, latch address
  • STEP 1 — Wait one clock cycle for memory read latency
  • STEP 2 — Capture data, assert destination write
  • STEP 3 — Advance addresses by 2 (16-bit word = 2 × 8-bit cells), decrement counter
• Asserts DONE when word count reaches zero, holds until RESET

Top Level (dma_top) — structural wrapper:

• Instantiates dma_logic and wires all external signals directly
• No additional logic — just port mapping

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Interface

Signal	Direction	Width	Description
clk	in	1	System clock
reset	in	1	Synchronous reset
start	in	1	Initiates transfer
src_start_addr	in	8-bit	Source start address
dst_start_addr	in	8-bit	Destination start address
length_words	in	8-bit	Number of 16-bit words to transfer
src_addr	out	8-bit	Current source address
dst_addr	out	8-bit	Current destination address
src_mode	out	1	Memory mode: 0=READ
dst_mode	out	1	Memory mode: 1=WRITE
done	out	1	Transfer complete flag

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Key Design Decisions

• Single clock read latency — an extra FSM step is added between asserting the read address and capturing data, accounting for synchronous memory behavior
• Address incrementation by 2 — since each word is 16-bit and each memory cell is 8-bit, addresses increment by 2 per word
• DONE latch — the DONE flag stays high after completion and only clears on RESET, ensuring the CPU can safely poll it