Name		Name	Last commit message	Last commit date
ARM.v		ARM.v
CPU_structure.png		CPU_structure.png
LICENSE		LICENSE
README.md		README.md
alu.v		alu.v
arm_tb_answer_1.txt		arm_tb_answer_1.txt
arm_tb_answer_2.txt		arm_tb_answer_2.txt
arm_tb_answer_3.txt		arm_tb_answer_3.txt
arm_tb_answer_4.txt		arm_tb_answer_4.txt
arm_tb_mem_data_1.txt		arm_tb_mem_data_1.txt
arm_tb_mem_data_2.txt		arm_tb_mem_data_2.txt
arm_tb_mem_data_3.txt		arm_tb_mem_data_3.txt
arm_tb_mem_data_4.txt		arm_tb_mem_data_4.txt
arm_tb_program_1.txt		arm_tb_program_1.txt
arm_tb_program_2.txt		arm_tb_program_2.txt
arm_tb_program_3.txt		arm_tb_program_3.txt
arm_tb_program_4.txt		arm_tb_program_4.txt
controller.v		controller.v
data_mem.v		data_mem.v
ins_mem.v		ins_mem.v
multi_4.v		multi_4.v
register_file.v		register_file.v
rotate.v		rotate.v
run.bat		run.bat
shift.v		shift.v
tb_ARM_1.v		tb_ARM_1.v
tb_ARM_2.v		tb_ARM_2.v
tb_ARM_3.v		tb_ARM_3.v
tb_ARM_4.v		tb_ARM_4.v
unsigned_extend.v		unsigned_extend.v

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A single cycle ARM CPU (32 bits)

This is a final project for LOGIC SYSTEM LABORATORY in NCKUEE.

Provides 4 testbenches for validation.
You can run through all testbenches by running run.bat (if you have already installed Icarus Verilog).

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A single cycle ARM CPU written in verilog.

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