Mixed-precision floating point units, wrapped in Chisel.

Floating point units (add, mul, FMA) for transprecision computing in arbitrary FP formats, wrapped and tested in Chisel. The verilog implementation is based on ETH's CVFPU.

• Organization: MICAS (KU Leuven)
• Maintainer: Robin Geens

Features ✨

• Modules
  • FpAddFp — floating‑point addition
  • FpMulFp — floating‑point multiplication
  • FpFmaFp — fused multiply‑add
  • All are implemented in a purely combinatorial way
• Mixed precision
  • Independent type selection per input/output
  • Supported sofar: FP8, FP16, BF16, FP32
  • To add new (arbitrary FP type):
    1. Create object that inherits from FpType
    2. Add type to fp_format_e and fp_encoding_t in src/main/resources/common_block/fpnew_pkg_snax.sv
    3. Add tests cases (and pray they work)
• Testing
  • Randomized tests
  • Mixed‑precision coverage

Repository layout

• src/main/scala/fp_unit/ — Chisel wrappers and type definitions
• src/test/scala/fp_unit/ — Test suites and reference utilities
• src/main/resources/ — Verilog source code