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[feat] Enforce semantics for write once memory (wom)#1834

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1560-feat-enforce-semantics-for-write-once-memory-wom
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[feat] Enforce semantics for write once memory (wom)#1834
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1560-feat-enforce-semantics-for-write-once-memory-wom

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@OlivierBBB OlivierBBB linked an issue Jun 2, 2026 that may be closed by this pull request
Signed-off-by: Olivier Bégassat <olivier.begassat.cours@gmail.com>
Signed-off-by: Olivier Bégassat <olivier.begassat.cours@gmail.com>
Signed-off-by: Olivier Bégassat <olivier.begassat.cours@gmail.com>
Signed-off-by: Olivier Bégassat <olivier.begassat.cours@gmail.com>
@OlivierBBB OlivierBBB force-pushed the 1560-feat-enforce-semantics-for-write-once-memory-wom branch from 5cf507a to 145c864 Compare June 2, 2026 22:00
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@OlivierBBB OlivierBBB force-pushed the 1560-feat-enforce-semantics-for-write-once-memory-wom branch from aaa745a to c0cc361 Compare June 2, 2026 22:12
@OlivierBBB OlivierBBB self-assigned this Jun 2, 2026
@OlivierBBB OlivierBBB marked this pull request as ready for review June 3, 2026 08:00
Copilot AI review requested due to automatic review settings June 3, 2026 08:00
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Pull request overview

This PR aims to introduce/enforce semantics for write-once memory (WOM) by adding specification docs (RAM/ROM/WOM) and beginning an implementation of memory-related MIR constraints in the ZkC constraints translator, along with a small unit-test fixture.

Changes:

  • Added markdown specifications for RAM/ROM/WOM constraint semantics and lookup interactions.
  • Refactored memory translation in pkg/zkc/constraints/translator.go to route ROM/WOM/RAM through a shared translateMemoryCommon() and added initial (partial) constraints.
  • Added a new unit test fixture and a test entry for it.

Reviewed changes

Copilot reviewed 15 out of 15 changed files in this pull request and generated 13 comments.

Show a summary per file
File Description
wom.md New WOM constraint specification (docs) including bus interaction pseudocode and lookup mapping.
rom.md New ROM constraint specification (docs).
ram.md New RAM constraint specification (docs) and discussion of finalization.
pkg/zkc/constraints/translator.go Implements shared memory translation and adds initial flag/timestamp constraints for memories.
pkg/ir/mir/constraint.go Adds placeholder constructors for send/receive constraints.
pkg/test/zkc_unit_test.go Adds a new unit test invoking the new _example fixture.
testdata/zkc/unit/_example.zkc New unit test program fixture.
testdata/zkc/unit/_example.accepts New expected I/O JSON for the _example fixture.
testdata/zkc/unit/_example_0.zkc Additional example fixture (not referenced by the new test entry).
pkg/zkc/compiler/parser/environment.go Receiver renaming cleanup for Environment methods.
pkg/zkc/compiler/codegen/statement.go Comment example formatting tweak (documentation-only).
pkg/zkc/compiler/ast/decl/decl.go Expanded Declaration doc comment.
pkg/schema/constraint/vanishing/constraint.go Comment punctuation tweak.
pkg/schema/constraint/ranged/constraint.go Comment punctuation tweak.
pkg/ir/hir/constraint.go Comment punctuation tweak.

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Comment on lines +132 to +134
memoryModule.AddRegisters(register.NewComputed("timestamp_read", timestampWidth, padding))
memoryModule.AddRegisters(register.NewComputed("timestamp_write", timestampWidth, padding))
memoryModule.AddRegisters(register.NewComputed("timestamp_delta", timestampWidth, padding))
Comment on lines +101 to +106
// Write once memory and read only memory are equivalent on the constraints level
func translateWriteOnceMemory[F field.Element[F]](
ctx schema.ModuleId, fm vm.InputOutputMemory[F]) mir.Module[F] {
var name = trace.ModuleName{Name: fm.Name(), Multiplier: 1}
return translateMemoryCommon(ctx, fm, name)
}
Comment thread pkg/ir/mir/constraint.go
Comment on lines +69 to +72
func NewSendConstraint[F field.Element[F]](handle string, sources []register.Id) Constraint[F] {
// TODO
return Constraint[F]{}
}
Comment thread pkg/ir/mir/constraint.go
Comment on lines +76 to +79
func NewReceiveConstraint[F field.Element[F]](handle string, sources []register.Id) Constraint[F] {
// TODO
return Constraint[F]{}
}
Comment on lines +86 to +87
// > var t tmp
// > tmp = f(...)
Comment thread rom.md
Comment on lines +62 to +66
// bus interactions
if WAS_ALREADY_WRITTEN_TO = true then
// address of ROM was written to at some point
snd( ADDRESS, 0, VALUE ) // initialization
rcv( ADDRESS, TIMESTAMP_READ, VALUE ) // finalization
Comment thread rom.md
Comment on lines +71 to +74
```rust
rcv( address, timestamp, is_written, value )
snd( address, timestamp, is_written, value )
```
Comment thread ram.md

### Triggering the finalization phase

To avoid ROM, WOM, and RAM all share the same issue wrt the logUpBus: if initialization/finalization isn't tightly constrained a memory cell can end up living many parallel lives. One constraint that removes this issue is to impose that these memory-types perform a single initialiazation/finalization event per address. Here's one way of doing this in our RISCV zkVM/zkc interpreter:
Comment thread ram.md

// executed at program end
if pc == MAX_UINT_64 {
// finaliztion of ROM's
Comment thread ram.md
snd( address, timestamp, value )
```

Any zkc module `MOD` that allows one to touch the WOM requires the following columns
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feat: enforce semantics for Write Once Memory (WOM)

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