v0.3: document vector lane mask p + staged V.ADD/V.PSEL

[zhoubot]

Updates ISA manual + staged Sail model for vector lane mask/predication bring-up.

Manual:

• Document LCFR.LaneNum (LCFR[19:16] = log2(vec_length)), vec_length derivation.
• Define block-local lane mask p initialization from B.DIM/B.ATTR, including DR=B.ATTR[26] strip-mining tail behavior.
• Clarify inactive lanes are unspecified; compilers must use V.PSEL for explicit merge.

Sail (staged):

• Add SSR LCFR storage (0x0024) and vec_length helper.
• Add block-local vec_p and p init logic.
• Minimal vt#0..qemu: repin runtime convergence and stabilize default tile gate #7 register file model (64 lanes x 32-bit packed).
• Implement V.ADD and V.PSEL semantics per bring-up rules.

Also extends manual generator so V.PSEL gets informative pseudocode similar to CSEL.