feat(skippy): wire bounded host-RAM L2 serving - #1855
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Caution Review failedThe pull request is closed. ℹ️ Recent review info⚙️ Run configurationConfiguration used: Organization UI Review profile: CHILL Plan: Advanced Run ID: 📒 Files selected for processing (31)
📝 WalkthroughWalkthroughThe change wires ChangesConfiguration and resolution
Estimated code review effort: 4 (Complex) | ~60 minutes Change: Feature Sequence Diagram(s)sequenceDiagram
participant Client
participant KvStageIntegration
participant StageL2
participant L2Tier
participant L3
Client->>KvStageIntegration: request prefix restore
KvStageIntegration->>StageL2: check exact-state entry
StageL2->>L2Tier: validate key, token count, and digest
L2Tier-->>StageL2: L2 hit or miss
alt L2 miss
KvStageIntegration->>L3: load durable exact state
L3-->>KvStageIntegration: payload and manifest
KvStageIntegration->>StageL2: consider L3 fill for promotion
else L2 hit
StageL2-->>KvStageIntegration: restore runtime state
end
Suggested reviewers: ✨ Finishing Touches📝 Generate docstrings
🧪 Generate unit tests (beta)
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Problem
The consolidated cache stack in #1838 contains a bounded host-RAM L2 store, but serving never creates, fills, consults, invalidates, or reports it.
model_fit.cache_ram_mibtherefore still fails at model load and every L1 miss goes directly to disk L3.Result
This wires an opt-in, stage-scoped L2 mirror into ordinary exact-state serving:
model_fit.cache_ram_mibreachesStageKvCacheConfig.l2_max_bytes; zero remains disabled;L2 is created only when an active local L3 tier exists. A positive L2 budget never creates an authority-free cache.
This is stacked on #1838 and should be rebased onto
mainafter that integration branch lands.Validation
Exact commit:
ce0741eb51913cc5b7af0bfdacc0c8a78fe66eaccargo test -p skippy-cache --lib— 265 passed, 2 ignoredcargo test -p skippy-server— 744 passed, 3 ignoredcargo test -p mesh-llm-config— 237 tests passed across the packagecargo test -p mesh-llm-host-runtime— 3,553 tests passed, 11 ignoredcargo test -p skippy-prompt— 24 passedcargo test -p skippy-protocol— 72 passedjust ci-validate— 1,453 passed, 9 skipped, plus repository consistency gatescargo fmt --all -- --check,just no-console-print, andgit diff --check366,375 nsversus12,090,875 ns), 50/50 L2 hits, zero evictionsBefore production rollout, run the required same-model Thoughtworks and c64/c128/c256 comparisons on Metal and discrete CUDA. The feature remains opt-in while that qualification is outstanding.
Summary by CodeRabbit
New Features
model_fit.cache_ram_mib.Bug Fixes
Documentation