0.5a

Performance improvement and implementation of low storage RK4 in phase-field (2 registers, 5 stages).
Reference: Carpenter and Kennedy, [Fourth-Order 2N-Storage Runge- Kutta Schemes, https://ntrs.nasa.gov/api/citations/19940028444/downloads/19940028444.pdf

0.5

Major changes include:

• Improved accuracy of the Poisson solver by fixing a minor bug in wavenumber computation.
• Corrected index mismatches in channel flow configurations.
• Tested the code with the latest NVIDIA HPC SDK versions 25.11 and CUDA 13.x.
• Modified the phase-field formulation to Rk4 + skew-symmetric-splitting, enabling the use of a finer grid with a smaller step size (0.51 eps/dx) for thinner interfaces.
• Refactored and optimized the code structure for better readability and maintainability.

0.4

🚀 Extension to wall-bounded turbulence and active/passive scalar
✅ Tested with NVIDIA HPC SDK versions 25.9
📄 Paper linked with this new version: https://doi.org/10.1016/j.cpc.2025.109956

0.3

Version 0.3

🚀 Major performance boost on both local and HPC clusters, achieved during the OpenACC CINECA Hackathon (up to 26× faster).
✅ Tested with NVIDIA HPC SDK versions 25.3 and 25.7.
🐛 Fixed minor issues in the Poisson solver and ACDI implementation.
📄 The paper associated with this code has been accepted and published open access: https://doi.org/10.1016/j.cpc.2025.109804