UART + Register Model Verification Testbench

Project: UVM / SystemVerilog – UART + Register Model Verification

---

Overview

This project implements a complete SystemVerilog UVM testbench for verifying UART communication and a register model (RAL).
The testbench includes UART agents, register adapters, sequences, and a scoreboard to ensure correct data transmission, reception, and register read/write operations.

Key features:

• UART Agent with driver and monitor:

  • Handles start, stop, and parity bits
  • Supports asynchronous reset
  • Configurable transmission speeds: 19200 and 115200 bps

• Test sequences:

  • Random transaction generation
  • Error injection in start, stop, and parity bits

• Register Model (RAL):

  • Two master/slave register blocks
  • Adapter classes (reg2bus / bus2reg)
  • Integrated with UART agents

• Scoreboard & Verification:

  • Compares transmitted/received data with register model
  • Supports layered architecture
  • Verifies correct read/write operations

• Final tests:

  • Top module and sequential tests
  • Logs UART transactions and register reads
  • Simulated in https://edaplayground.com/x/fzpd

---

Architecture

Flow: Test (write/read registers)
↓
Register Model (RAL)
↓
reg2bus / bus2reg Adapter
↓
Reg Agent (Sequencer + Driver)
↓
UART Agent (Sequencer + Driver) ↓
TX Line → DUT
RX Line ← UART Agent Monitor
↓
Scoreboard / Verification

Usage

1. Open the project in EDA Playground via the link above.
2. Run the simulation to see UART transactions and register read/write operations logged.
3. Inspect the environment diagram (env.png) for component connections.