UVM-ALU

Simple ALU has be designed with 4 different modes of operation.

TESTBENCH ARCHITECTURE

Name		Name	Last commit message	Last commit date
Latest commit History 16 Commits
README.md		README.md
agent.sv		agent.sv
driver.sv		driver.sv
dut.sv		dut.sv
environment.sv		environment.sv
interface.sv		interface.sv
monitor.sv		monitor.sv
scoreboard.sv		scoreboard.sv
seq_item.sv		seq_item.sv
sequence.sv		sequence.sv
sequencer.sv		sequencer.sv
test.sv		test.sv
testbench.sv		testbench.sv

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