Add hardware design files for Backplane PCBs

[FerretCode]

Summary

What changed and why:

Created hardware design files for the backplane PCBs, with each project corresponding to a different size of CubeSat (e.g., 1U, 2U, 3U backplanes)

Related issue/ticket (if any):

#89

Type of Change

• Hardware - schematic
• Hardware - layout
• Firmware - new service/module
• Firmware - refactor of existing service/module
• Documentation only
• Other:

Affected subsystem(s):

Backplane

Requirements Traceability

• This change is covered by an existing requirement in the subsystem's information doc
• This change requires a new or updated requirement in the information doc (link/describe below)
• This change requires an update to the CDS-compliance checklist (see the Preliminary Hardware Design Guidelines)

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Hardware Checklist

Reference: Preliminary Hardware Design Guidelines, Schematic & Layout Design Guidelines

Schematic

• All nets labeled, no floating/unlabeled nets
• Decoupling capacitors placed per datasheet for every new/changed IC
• Pull-up/pull-down resistors present on shared buses (I2C, reset, boot)
• Test points/headers added for key signals (UART, RESET, SWD/JTAG, I2C, SPI) if newly introduced
• Protection added where applicable (fuses, TVS, reverse-polarity, ESD) on any new external interface
• Components derated per team policy (voltage/current/power margin applied, not just worst-case survival)
• ERC is clean: no errors, no unresolved warnings
• Peer schematic review completed by someone other than the author

Layout

• Stackup/impedance requirements unaffected, or explicitly re-verified if changed
• Return paths remain short/continuous; ground plane not split
• Decoupling caps placed close to their ICs
• Trace widths verified against current requirements (via KiCad calculator or equivalent)
• Silkscreen updated: polarity marks, orientation dots, version/revision number bumped
• Assembly file exported and spot-checked for obvious placement errors
• DFM check: in-stock parts used, no exotic footprints introduced without discussion

CDS / Mission Compliance (only if this change affects envelope, mass, power architecture, RBF, deployment switches, or RF)

• Reviewed against CDS-compliance checklist in Preliminary Hardware Design Guidelines
• No new CDS deviation introduced, or deviation documented and routed for approval

ATP / Bring-Up Impact

• This change affects a board/unit that already has a released ATP: ATP updated or flagged for update
• This change was verified via bring-up/test procedure (attach results or link)
• No impact to existing ATP

Deviations

List any deviation from the design guideline docs introduced by this PR, with justification. Leave blank if none.

Guideline doc	Deviation	Justification	Approved by

Reviewer Sign-off

• I reviewed this PR against the relevant checklist section(s) above, not just the diff
• Any checked-but-not-actually-verified items were flagged and discussed with the author
• No open anomalies/deviations without an approver

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