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Omalya negation fix #19

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OmalyaV Jun 15, 2023
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OmalyaV Jun 15, 2023
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Binary file modified Lab9/Lab9.sim/sim_1/behav/xsim/TB_NanoProcessor_behav.wdb
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2 changes: 1 addition & 1 deletion Lab9/Lab9.sim/sim_1/behav/xsim/compile.bat
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Expand Up @@ -6,7 +6,7 @@ REM Filename : compile.bat
REM Simulator : Xilinx Vivado Simulator
REM Description : Script for compiling the simulation design source files
REM
REM Generated by Vivado on Thu Jun 15 10:56:22 +0530 2023
REM Generated by Vivado on Thu Jun 15 14:34:10 +0530 2023
REM SW Build 2258646 on Thu Jun 14 20:03:12 MDT 2018
REM
REM Copyright 1986-2018 Xilinx, Inc. All Rights Reserved.
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2 changes: 1 addition & 1 deletion Lab9/Lab9.sim/sim_1/behav/xsim/elaborate.bat
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Expand Up @@ -6,7 +6,7 @@ REM Filename : elaborate.bat
REM Simulator : Xilinx Vivado Simulator
REM Description : Script for elaborating the compiled design
REM
REM Generated by Vivado on Thu Jun 15 10:56:24 +0530 2023
REM Generated by Vivado on Thu Jun 15 14:34:12 +0530 2023
REM SW Build 2258646 on Thu Jun 14 20:03:12 MDT 2018
REM
REM Copyright 1986-2018 Xilinx, Inc. All Rights Reserved.
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2 changes: 1 addition & 1 deletion Lab9/Lab9.sim/sim_1/behav/xsim/simulate.bat
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Expand Up @@ -6,7 +6,7 @@ REM Filename : simulate.bat
REM Simulator : Xilinx Vivado Simulator
REM Description : Script for simulating the design by launching the simulator
REM
REM Generated by Vivado on Thu Jun 15 10:56:26 +0530 2023
REM Generated by Vivado on Thu Jun 15 14:34:14 +0530 2023
REM SW Build 2258646 on Thu Jun 14 20:03:12 MDT 2018
REM
REM Copyright 1986-2018 Xilinx, Inc. All Rights Reserved.
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Binary file modified Lab9/Lab9.sim/sim_1/behav/xsim/xsim.dir/TB_NanoProcessor_behav/obj/xsim_0.win64.obj
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2 changes: 1 addition & 1 deletion Lab9/Lab9.sim/sim_1/behav/xsim/xsim.dir/TB_NanoProcessor_behav/webtalk/.xsim_webtallk.info
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@@ -1,5 +1,5 @@
1686806304
1686806426
42
45
1
c036f6d3b11b46258ae2394c8cc98222
28 changes: 9 additions & 19 deletions Lab9/Lab9.sim/sim_1/behav/xsim/xsim.dir/TB_NanoProcessor_behav/webtalk/xsim_webtalk.tcl
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@@ -1,6 +1,6 @@
webtalk_init -webtalk_dir D:/projects/NanoProcessor-Team-93/Lab9/Lab9.sim/sim_1/behav/xsim/xsim.dir/TB_NanoProcessor_behav/webtalk/
webtalk_register_client -client project
webtalk_add_data -client project -key date_generated -value "Thu Jun 15 10:56:26 2023" -context "software_version_and_target_device"
webtalk_add_data -client project -key date_generated -value "Thu Jun 15 14:38:25 2023" -context "software_version_and_target_device"
webtalk_add_data -client project -key product_version -value "XSIM v2018.2 (64-bit)" -context "software_version_and_target_device"
webtalk_add_data -client project -key build_version -value "2258646" -context "software_version_and_target_device"
webtalk_add_data -client project -key os_platform -value "WIN64" -context "software_version_and_target_device"
Expand All @@ -14,29 +14,19 @@ webtalk_add_data -client project -key target_package -value "not_applicable" -co
webtalk_add_data -client project -key target_speed -value "not_applicable" -context "software_version_and_target_device"
webtalk_add_data -client project -key random_id -value "91ea39e5fcfc55108cea2d38c5723418" -context "software_version_and_target_device"
webtalk_add_data -client project -key project_id -value "c036f6d3b11b46258ae2394c8cc98222" -context "software_version_and_target_device"
webtalk_add_data -client project -key project_iteration -value "41" -context "software_version_and_target_device"
webtalk_add_data -client project -key project_iteration -value "44" -context "software_version_and_target_device"
webtalk_add_data -client project -key os_name -value "Microsoft Windows 8 or later , 64-bit" -context "user_environment"
webtalk_add_data -client project -key os_release -value "major release (build 9200)" -context "user_environment"
webtalk_add_data -client project -key cpu_name -value "11th Gen Intel(R) Core(TM) i7-1165G7 @ 2.80GHz" -context "user_environment"
webtalk_add_data -client project -key cpu_speed -value "1690 MHz" -context "user_environment"
webtalk_add_data -client project -key total_processors -value "1" -context "user_environment"
webtalk_add_data -client project -key system_ram -value "8.000 GB" -context "user_environment"
webtalk_register_client -client xsim
webtalk_add_data -client xsim -key File_Counter -value "25" -context "xsim\\command_line_options"
webtalk_add_data -client xsim -key Command -value "xelab" -context "xsim\\command_line_options"
webtalk_add_data -client xsim -key Vhdl2008 -value "false" -context "xsim\\command_line_options"
webtalk_add_data -client xsim -key GenDLL -value "false" -context "xsim\\command_line_options"
webtalk_add_data -client xsim -key SDFModeling -value "false" -context "xsim\\command_line_options"
webtalk_add_data -client xsim -key HWCosim -value "false" -context "xsim\\command_line_options"
webtalk_add_data -client xsim -key DPI_Used -value "false" -context "xsim\\command_line_options"
webtalk_add_data -client xsim -key Debug -value "typical" -context "xsim\\command_line_options"
webtalk_add_data -client xsim -key Simulation_Image_Code -value "126 KB" -context "xsim\\usage"
webtalk_add_data -client xsim -key Simulation_Image_Data -value "10 KB" -context "xsim\\usage"
webtalk_add_data -client xsim -key Total_Nets -value "0" -context "xsim\\usage"
webtalk_add_data -client xsim -key Total_Processes -value "180" -context "xsim\\usage"
webtalk_add_data -client xsim -key Total_Instances -value "58" -context "xsim\\usage"
webtalk_add_data -client xsim -key Xilinx_HDL_Libraries_Used -value "secureip " -context "xsim\\usage"
webtalk_add_data -client xsim -key Compiler_Time -value "0.22_sec" -context "xsim\\usage"
webtalk_add_data -client xsim -key Compiler_Memory -value "53468_KB" -context "xsim\\usage"
webtalk_transmit -clientid 2677486177 -regid "" -xml D:/projects/NanoProcessor-Team-93/Lab9/Lab9.sim/sim_1/behav/xsim/xsim.dir/TB_NanoProcessor_behav/webtalk/usage_statistics_ext_xsim.xml -html D:/projects/NanoProcessor-Team-93/Lab9/Lab9.sim/sim_1/behav/xsim/xsim.dir/TB_NanoProcessor_behav/webtalk/usage_statistics_ext_xsim.html -wdm D:/projects/NanoProcessor-Team-93/Lab9/Lab9.sim/sim_1/behav/xsim/xsim.dir/TB_NanoProcessor_behav/webtalk/usage_statistics_ext_xsim.wdm -intro "<H3>XSIM Usage Report</H3><BR>"
webtalk_add_data -client xsim -key Command -value "xsim" -context "xsim\\command_line_options"
webtalk_add_data -client xsim -key trace_waveform -value "true" -context "xsim\\usage"
webtalk_add_data -client xsim -key runtime -value "1 us" -context "xsim\\usage"
webtalk_add_data -client xsim -key iteration -value "3" -context "xsim\\usage"
webtalk_add_data -client xsim -key Simulation_Time -value "0.00_sec" -context "xsim\\usage"
webtalk_add_data -client xsim -key Simulation_Memory -value "7332_KB" -context "xsim\\usage"
webtalk_transmit -clientid 4131901873 -regid "" -xml D:/projects/NanoProcessor-Team-93/Lab9/Lab9.sim/sim_1/behav/xsim/xsim.dir/TB_NanoProcessor_behav/webtalk/usage_statistics_ext_xsim.xml -html D:/projects/NanoProcessor-Team-93/Lab9/Lab9.sim/sim_1/behav/xsim/xsim.dir/TB_NanoProcessor_behav/webtalk/usage_statistics_ext_xsim.html -wdm D:/projects/NanoProcessor-Team-93/Lab9/Lab9.sim/sim_1/behav/xsim/xsim.dir/TB_NanoProcessor_behav/webtalk/usage_statistics_ext_xsim.wdm -intro "<H3>XSIM Usage Report</H3><BR>"
webtalk_terminate
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2 changes: 1 addition & 1 deletion Lab9/Lab9.sim/sim_1/behav/xsim/xsim.dir/TB_NanoProcessor_behav/xsim.rlx
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@@ -1,6 +1,6 @@

{
crc : 7179170433809754358 ,
crc : 7179170434661855856 ,
ccp_crc : 0 ,
cmdline : " -wto c036f6d3b11b46258ae2394c8cc98222 --incr --debug typical --relax --mt 2 -L xil_defaultlib -L secureip --snapshot TB_NanoProcessor_behav xil_defaultlib.TB_NanoProcessor" ,
buildDate : "Jun 14 2018" ,
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8 changes: 4 additions & 4 deletions Lab9/Lab9.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/xil_defaultlib.rlx
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Expand Up @@ -10,16 +10,16 @@ D:/projects/NanoProcessor-Team-93/Lab9/Lab9.srcs/sources_1/new/Decoder_2_to_4.vh
D:/projects/NanoProcessor-Team-93/Lab9/Lab9.srcs/sources_1/new/Decoder_3_to_8.vhd,1686232567,vhdl,,,,decoder_3_to_8,,,,,,,,
D:/projects/NanoProcessor-Team-93/Lab9/Lab9.srcs/sources_1/new/FA.vhd,1686232567,vhdl,,,,fa,,,,,,,,
D:/projects/NanoProcessor-Team-93/Lab9/Lab9.srcs/sources_1/new/HA.vhd,1686232567,vhdl,,,,ha,,,,,,,,
D:/projects/NanoProcessor-Team-93/Lab9/Lab9.srcs/sources_1/new/Instruction_decoder.vhd,1686806263,vhdl,,,,instruction_decoder,,,,,,,,
D:/projects/NanoProcessor-Team-93/Lab9/Lab9.srcs/sources_1/new/LUT_16_7.vhd,1686806695,vhdl,,,,lut_16_7,,,,,,,,
D:/projects/NanoProcessor-Team-93/Lab9/Lab9.srcs/sources_1/new/Instruction_decoder.vhd,1686819780,vhdl,,,,instruction_decoder,,,,,,,,
D:/projects/NanoProcessor-Team-93/Lab9/Lab9.srcs/sources_1/new/LUT_16_7.vhd,1686819780,vhdl,,,,lut_16_7,,,,,,,,
D:/projects/NanoProcessor-Team-93/Lab9/Lab9.srcs/sources_1/new/MUX_2_way_3_bit.vhd,1686232567,vhdl,,,,mux_2_way_3_bit,,,,,,,,
D:/projects/NanoProcessor-Team-93/Lab9/Lab9.srcs/sources_1/new/MUX_2_way_4_bits.vhd,1686232567,vhdl,,,,mux_2_way_4_bit,,,,,,,,
D:/projects/NanoProcessor-Team-93/Lab9/Lab9.srcs/sources_1/new/MUX_8_way_4_bit.vhd,1686232567,vhdl,,,,mux_8_way_4_bit,,,,,,,,
D:/projects/NanoProcessor-Team-93/Lab9/Lab9.srcs/sources_1/new/NanoProcessor.vhd,1686232567,vhdl,,,,nanoprocessor,,,,,,,,
D:/projects/NanoProcessor-Team-93/Lab9/Lab9.srcs/sources_1/new/Program_Counter.vhd,1686232567,vhdl,,,,program_counter,,,,,,,,
D:/projects/NanoProcessor-Team-93/Lab9/Lab9.srcs/sources_1/new/RCA_Adder_Subtractor.vhd,1686232567,vhdl,,,,rca_adder_subtractor,,,,,,,,
D:/projects/NanoProcessor-Team-93/Lab9/Lab9.srcs/sources_1/new/ROM.vhd,1686806592,vhdl,,,,rom,,,,,,,,
D:/projects/NanoProcessor-Team-93/Lab9/Lab9.srcs/sources_1/new/ROM.vhd,1686819780,vhdl,,,,rom,,,,,,,,
D:/projects/NanoProcessor-Team-93/Lab9/Lab9.srcs/sources_1/new/Register_Bank.vhd,1686232567,vhdl,,,,register_bank,,,,,,,,
D:/projects/NanoProcessor-Team-93/Lab9/Lab9.srcs/sources_1/new/Registers.vhd,1686232567,vhdl,,,,registers,,,,,,,,
D:/projects/NanoProcessor-Team-93/Lab9/Lab9.srcs/sources_1/new/Slow_Clk.vhd,1686806779,vhdl,,,,slow_clk,,,,,,,,
D:/projects/NanoProcessor-Team-93/Lab9/Lab9.srcs/sources_1/new/Slow_Clk.vhd,1686819848,vhdl,,,,slow_clk,,,,,,,,
D:/projects/NanoProcessor-Team-93/Lab9/Lab9.srcs/sources_1/new/adder_3bit.vhd,1686232567,vhdl,,,,adder_3bit,,,,,,,,
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4 changes: 2 additions & 2 deletions Lab9/Lab9.srcs/sources_1/new/Slow_Clk.vhd
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Expand Up @@ -44,8 +44,8 @@ begin
process (Clk_in) begin
if (rising_edge(Clk_in)) then
count <= count +1;
if (count = 4) then
--if (count = 50000000) then
--if (count = 4) then
if (count = 50000000) then
clk_status <= not clk_status;
Clk_out <= clk_status;
count <= 1;
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8 changes: 5 additions & 3 deletions Lab9/Lab9.xpr
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Expand Up @@ -33,7 +33,7 @@
<Option Name="DSAVendor" Val="xilinx"/>
<Option Name="DSABoardId" Val="basys3"/>
<Option Name="DSANumComputeUnits" Val="60"/>
<Option Name="WTXSimLaunchSim" Val="55"/>
<Option Name="WTXSimLaunchSim" Val="56"/>
<Option Name="WTModelSimLaunchSim" Val="0"/>
<Option Name="WTQuestaLaunchSim" Val="0"/>
<Option Name="WTIesLaunchSim" Val="0"/>
Expand Down Expand Up @@ -293,15 +293,16 @@
</Simulator>
</Simulators>
<Runs Version="1" Minor="10">
<Run Id="synth_1" Type="Ft3:Synth" SrcSet="sources_1" Part="xc7a35tcpg236-1" ConstrsSet="constrs_1" Description="Vivado Synthesis Defaults" WriteIncrSynthDcp="false" State="current" IncludeInArchive="true">
<Run Id="synth_1" Type="Ft3:Synth" SrcSet="sources_1" Part="xc7a35tcpg236-1" ConstrsSet="constrs_1" Description="Vivado Synthesis Defaults" WriteIncrSynthDcp="false" State="current" Dir="$PRUNDIR/synth_1" IncludeInArchive="true">
<Strategy Version="1" Minor="2">
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2018"/>
<Step Id="synth_design"/>
</Strategy>
<GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
<ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2018"/>
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
</Run>
<Run Id="impl_1" Type="Ft2:EntireDesign" Part="xc7a35tcpg236-1" ConstrsSet="constrs_1" Description="Default settings for Implementation." WriteIncrSynthDcp="false" State="current" SynthRun="synth_1" IncludeInArchive="true" GenFullBitstream="true">
<Run Id="impl_1" Type="Ft2:EntireDesign" Part="xc7a35tcpg236-1" ConstrsSet="constrs_1" Description="Default settings for Implementation." WriteIncrSynthDcp="false" State="current" Dir="$PRUNDIR/impl_1" SynthRun="synth_1" IncludeInArchive="true" GenFullBitstream="true">
<Strategy Version="1" Minor="2">
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2018"/>
<Step Id="init_design"/>
Expand All @@ -314,6 +315,7 @@
<Step Id="post_route_phys_opt_design"/>
<Step Id="write_bitstream"/>
</Strategy>
<GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
<ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2018"/>
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
</Run>
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