ONNXim changes

example/resnet18_infr.json

@@ -0,0 +1,16 @@
+{
+  "models": [
+    {
+      "name": "resnet18",
+      "trace_file": "resnet18.csv",
+      "onnx_file": "./models/resnet18/resnet18.onnx",
+      "input_shape": [1, 3, 224, 224],
+      "num_classes": 1000,
+	"batch_size": 1,
+      "scheduler": "simple",
+      "scheduler_config": {
+        "max_batch_size": 8
+      }
+    }
+  ]
+}

scripts/generate_cnn_trace.py

@@ -0,0 +1,24 @@
+import csv
+import random
+
+# Number of trace entries
+num_rows = 20
+
+# Initialize CSV
+with open('./traces/resnet18.csv', 'w', newline='') as csvfile:
+    writer = csv.writer(csvfile)
+    writer.writerow(['time', 'prompt_length', 'target_length', 'cached_length'])
+
+    current_time = 0
+    for _ in range(num_rows):
+        # Simulate ResNet18 input
+        batch_size = random.choice([1, 2, 4, 8])
+        input_pixels = 224 * 224 * 3  # total pixels in image
+        prompt_length = input_pixels * batch_size
+        target_length = 1000  # number of output classes in ImageNet
+        cached_length = 0  # ResNet18 usually doesn't use cached states
+
+        writer.writerow([current_time, prompt_length, target_length, cached_length])
+
+        # Increment time by random interval (simulate requests)
+        current_time += random.randint(50, 200)  # ms

src/Common.h

@@ -1,3 +1,4 @@
+
 #pragma once
 
 #include <robin_hood.h>
@@ -29,6 +30,8 @@
 
 using json = nlohmann::json;
 
+struct Tensor;
+
 typedef uint64_t addr_type;
 typedef uint64_t cycle_type;
 
@@ -44,7 +47,8 @@ typedef struct {
   cycle_type dram_enter_cycle;
   cycle_type dram_finish_cycle;
   int buffer_id;
-} MemoryAccess;
+  addr_type tensor_id;   // if it doesnt work then id from instruciton should be uint64_t like addr_type so we use uint64_t instead of 32
+             } MemoryAccess;
 
 enum class Opcode {
   MOVIN,
@@ -72,8 +76,9 @@ typedef struct {
   Opcode opcode;
   cycle_type start_cycle;
   cycle_type finish_cycle;
-  std::string id;
+  std::string id; //changes this here since id in instruction.h is uint32_t which is passed by _outputid in global.cc
   std::vector<std::string> dependent_ids;
+  uint32_t tensor_id;
   std::string dest_id;
   addr_type dest_addr;
   uint32_t size;          // Used for sram allocation. Multiple of _config.dram_req_size
@@ -117,6 +122,7 @@ struct Tile {
 
   TileStat stat;
   std::deque<std::unique_ptr<Instruction>> instructions;
+  uint32_t tensor_id; //<-- added this
   bool accum;
   bool skip;
   int spad_id;
@@ -144,4 +150,4 @@ uint32_t ceil_div(uint32_t src, uint32_t div);
 
 std::vector<uint32_t> parse_dims(const std::string &str);
 
-std::string dims_to_string(const std::vector<uint32_t> &dims);
+std::string dims_to_string(const std::vector<uint32_t> &dims);

src/Core.cc

@@ -1,9 +1,12 @@
+
 #include "Core.h"
 #include "SystolicWS.h"
 #include "SystolicOS.h"
 
 #include "helper/HelperFunctions.h"
 
+struct Tensor;
+
 std::unique_ptr<Core> Core::create(uint32_t id, SimulationConfig config) {
   if (config.core_config[id].core_type == CoreType::SYSTOLIC_WS) {
     return std::make_unique<SystolicWS>(id, config);
@@ -342,6 +345,7 @@ void Core::handle_ld_inst_queue() {
       }
       for (addr_type addr : front->src_addrs) {
         assert(front->base_addr != GARBEGE_ADDR);
+
         MemoryAccess *access =
             new MemoryAccess({.id = generate_mem_access_id(),
                               .dram_address = addr + front->base_addr,
@@ -351,7 +355,9 @@ void Core::handle_ld_inst_queue() {
                               .request = true,
                               .core_id = _id,
                               .start_cycle = _core_cycle,
-                              .buffer_id = buffer_id});
+                              .buffer_id = buffer_id,
+                               .tensor_id= front->dest_addr //id is from output_id tensor
+                            });
         _request_queue.push(access);
       }
       _ld_inst_queue.pop();
@@ -364,7 +370,7 @@ void Core::handle_ld_inst_queue() {
 void Core::handle_st_inst_queue() {
   if (!_st_inst_queue.empty()) {
     std::unique_ptr<Instruction> front = std::move(_st_inst_queue.front());
-    if (front->opcode == Opcode::MOVOUT || front->opcode == Opcode::MOVOUT_POOL) {
+       if (front->opcode == Opcode::MOVOUT || front->opcode == Opcode::MOVOUT_POOL) {
       Sram *buffer;
       int buffer_id;
       if (front->dest_addr >= ACCUM_SPAD_BASE) {
@@ -386,7 +392,10 @@ void Core::handle_st_inst_queue() {
                               .request = true,
                               .core_id = _id,
                               .start_cycle = _core_cycle,
-                              .buffer_id = buffer_id};
+                              .buffer_id = buffer_id,
+                             .tensor_id = front->dest_addr////id is from input_id in tensor
+
+};
           _waiting_write_reqs++;
           _request_queue.push(access);
         }

src/Instruction.h

@@ -25,7 +25,7 @@ class Instruction {
   enum class Type {
     LD_INST, ST_INST, EXE_INST
   };
-  uint32_t id; 
+  std::string id;  //change
   Opcode opcode;
   Type type;
   size_t tile_size;

src/Model.cc

@@ -31,8 +31,9 @@ Model::Model(json model_config, SimulationConfig config, std::string name)
 }
 
 Tensor* Model::get_tensor(uint32_t id) {
-  return _tensor_map[id].get();
-}
+    return _tensor_map[id].get();
+    }
+
 
 Tensor* Model::find_tensor(std::string name) {
   for(auto const& [key, val]: _tensor_map) {
@@ -122,19 +123,28 @@ void Model::initialize_model(std::vector<std::unique_ptr<Tensor>>& weight_table)
     }
   }
 
-  for(auto& [key, val] : _operation_map) {
-    /* Attention is speacial case */
+for (auto& [key, val] : _operation_map) {
+    /* Attention is special case */
     if (val->get_optype() == "Attention") {
-      Attention* attention_node = static_cast<Attention*>(val.get());
-      attention_node->initialize_onnx_tiles(_mapping_table);
-      int projection_id = attention_node->_projection_node->get_id();
-      _operation_map[projection_id] = std::move(std::unique_ptr<GemmWS>(attention_node->_projection_node));
-      _operation_map[projection_id]->initialize_tiles(_mapping_table);
-    }
-    else {
-      val->initialize_tiles(_mapping_table);
+        Attention* attention_node = static_cast<Attention*>(val.get());
+
+        // ✅ get the output tensor id and make a string version of it
+        uint32_t tensor_id_str;
+        if (!attention_node->_outputs.empty()) {
+            tensor_id_str = attention_node->_outputs.back();
+        }
+
+        // ✅ pass it to the specialized initializer
+        attention_node->initialize_onnx_tiles(_mapping_table, tensor_id_str);
+
+        int projection_id = attention_node->_projection_node->get_id();
+        _operation_map[projection_id] = std::move(std::unique_ptr<GemmWS>(attention_node->_projection_node));
+        _operation_map[projection_id]->initialize_tiles(_mapping_table);
+    } else {
+        val->initialize_tiles(_mapping_table);
     }
-  }
+}
+
 
   for (auto& [key, val]: _operation_map) {
     if(val->check_executable()) {
@@ -249,4 +259,23 @@ void Model::prepare_regressive() {
   nr_skip = 0;
   _start_time = 0;
   _started = false;
-}
+}
+extern std::unordered_map<uint32_t, TensorInfo> g_tensor_addr_map;
+extern std::mutex g_tensor_map_mutex;
+
+void Model::tensor_track(uint64_t dram_addr) {
+    std::lock_guard<std::mutex> lock(g_tensor_map_mutex);
+
+    for (auto& [id, info] : g_tensor_addr_map) {
+        if (dram_addr >= info.start_addr && dram_addr < info.end_addr) {
+            spdlog::info("DRAM access 0x{:x} → TensorID={} Name={} Range=[0x{:x}-0x{:x}) Size={}",
+                         dram_addr, id, info.name, info.start_addr, info.end_addr, info.size);
+            return;
+        }
+    }
+
+    spdlog::info("DRAM access 0x{:x} → [no matching tensor found]", dram_addr);
+}
+
+
+

src/Model.h

@@ -18,7 +18,10 @@ class Model {
     uint32_t get_root_node_id() { return _root_node_id; }
     void add_tensor(std::unique_ptr<Tensor> tensor);
     void set_layer_finish(uint32_t id); 
-
+    //added
+   void tensor_track(uint64_t tensor_id);
+
+//end
     std::string get_name() { return _name; }
     uint32_t executable_layer_size();
     Operation* get_executable_tile();

src/SimulationConfig.h

@@ -69,6 +69,8 @@ struct SimulationConfig {
   uint32_t precision;
   uint32_t full_precision = 4;
   std::string layout;
+//added this here only
+uint32_t vector_process_bit = 256; // added line
 
   /*
    * This map stores the partition information: <partition_id, core_id>