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  • Student at Tokyo Metropolitan College of Industrial Technology
  • Tokyo, Japan
  • 11:08 (UTC +09:00)

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  1. opensusi-tr10-balanced-ternary-logic opensusi-tr10-balanced-ternary-logic Public

    Balanced ternary logic gates and a 1-trit multiply-add slice for OpenSUSI TR-1um, with Xschem schematics, KLayout layouts and SPICE verification.

    Python

  2. opensusi-tr10-ishi-vga opensusi-tr10-ishi-vga Public

    ISHI logo VGA core for OpenSUSI TR-1um: RGB111, 7-terminal half-slot design, layout and verified submission

    Python

  3. opensusi-tr10-penguin-inverter opensusi-tr10-penguin-inverter Public

    OpenSUSI TR-1um inverter with Metal2 penguin silicon art

  4. opensusi-tr10-sram512 opensusi-tr10-sram512 Public

    512-bit (16x32) 6T SRAM for OpenSUSI TR-1um: schematics, testbenches, layout and verification.

    Python

  5. tr1um_gds_viewer tr1um_gds_viewer Public

    Forked from TinyTapeout/tinytapeout_gds_viewer

    Browser-based 3D/2D GDS viewer for OpenSUSI TR-1um, forked from Tiny Tapeout GDS Viewer

    JavaScript