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Purelikeic/README.md

Welcome aboard my code station 🚀

I am Zhijie Zhao, a master's student at the School of Integrated Circuits, Huazhong University of Science and Technology (HUST). I work on digital IC design and processor microarchitecture, currently focusing on RISC-V processors, cache subsystems, and coherence. I am passionate about research in computer architecture, from cores and caches to the system stack around them.

I am the captain of this ship. This ship 🛰️ sails at 27,580 km/h (or 17,130 mph). Crazy, isn't it? Well grab the firm handle closest to you because we are gonna go warp speed to know my universe.

Click Here to enter the Warp Speed and know more about my universe!

  • 🌌 I’m currently working on cache microarchitecture, coherence interfaces, and RISC-V processor / SoC bring-up
  • 🔭 I’m currently learning processor cores, memory hierarchy, and system-level validation
  • 👯 I’m looking to collaborate on projects related to (but not limited to) RISC-V, cache design, coherence, and digital IC frontend
  • ✨ Pronouns: He/him
  • 🛸 Fun fact: I like chasing a cache miss from software all the way down to the RTL waveform
  • 📫 How to reach me: GitHub · z.zhijie@outlook.com

Research interests:

  • Processor microarchitecture: RISC-V pipelines, branch prediction, bypassing, exceptions and interrupts
  • Cache and memory hierarchy: ICache / DCache / L2, MSHR, directory, replacement and prefetch
  • Cache coherence: CHI / TileLink / ACE style interfaces, probe, refill and writeback
  • Digital IC frontend: Chisel / Verilog RTL, simulation, FPGA prototype, and software-hardware co-debug

Languages and Tools:

RISC-V Python C C++ Chisel Linux Git Shell

Chisel Verilog SystemVerilog AXI4 TileLink CHI Verilator Yosys GTKWave FPGA

Zhijie's github stats

We have sped and warped through my universe. Want to unveil your own universe? Contact me at: GitHub Email

We're made of star stuff. We are a way for the cosmos to know itself- Carl Sagan

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