Support SM121 (NVIDIA GB10 / DGX Spark) via SM120 kernels - #33
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Support SM121 (NVIDIA GB10 / DGX Spark) via SM120 kernels#33zhachar14h-cell wants to merge 1 commit into
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Route compute version "12.1" (NVIDIA GB10, DGX Spark) to the existing SM120 Blackwell kernels. GB10 (sm_121a) belongs to the same consumer Blackwell SM family as SM120; the TileLang kernels JIT-compile and run correctly on it. Validated on a DGX Spark (GB10, CUDA 13.0, PyTorch 2.11, tilelang 0.1.9): - tests/test_gdr_unit.py forward cases pass against the float64 reference (53 passed), including auto_cp and cp_cache variants - tests/test_sm120_backward_disabled.py passes (backward stays gated) - deployed in vLLM 0.25 serving Qwen3.6-35B-A3B (hybrid GDN) as the GDN chunked-prefill kernel: numerics match the FLA Triton reference (max abs diff 7e-4 on outputs, 5e-3 on final states), T=8192 varlen kernel latency 7.19ms -> 1.62ms (4.45x), end-to-end TTFT -10% Also skip the backward-dependent mixed-CP test on SM120/SM121 (backward is disabled there by design) and fix stale supported-arch messages in cp_context.py which predated SM120 support.
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Route compute version "12.1" (NVIDIA GB10, DGX Spark) to the existing SM120 Blackwell kernels. GB10 (sm_121a) belongs to the same consumer Blackwell SM family as SM120; the TileLang kernels JIT-compile and run correctly on it.
Validated on a DGX Spark (GB10, CUDA 13.0, PyTorch 2.11, tilelang 0.1.9):
Also skip the backward-dependent mixed-CP test on SM120/SM121 (backward is disabled there by design) and fix stale supported-arch messages in cp_context.py which predated SM120 support.