[DSv4][P5-4] MXFP8×MXFP4 Routed Expert grouped GEMM: strict CUDA kernel

[Bignonia7]

Summary

P5-4 (#61): fc1/fc2 frozen base GEMM for routed experts — MXFP8 activation × MXFP4 frozen weight.

What's included

• csrc/cuda/moe/mxfp8_mxfp4_grouped_gemm.cu — hand-written strict FFMA kernel (fwd + dX-only bwd). MXFP4 weights stay packed; dequant happens in register/smem only. Byte-exact vs oracle-fp32-serial-v1.
• rl_engine/moe/provider.py — CudaP5GemmProvider fail-closed adapter + "cuda" alias; provenance() reports kernel fingerprint mxfp8-mxfp4-grouped-gemm-strict-v1.

Notes

• Backward writes dX only (base weights frozen, no dW).
• expert_tensor_parallel_size = 1.
• WGMMA performance path deferred to a later PR (SM90 fp8 WGMMA has no FP4 operand and reduced-precision accumulation, so it cannot be byte-exact here).

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[KJLdefeated]

Hi @Bignonia7, can you implement a Triton version of this kernel?