[AMDGPU] Give 4-cycle gfx1250 WMMA its own co-execution hazard category#3197
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kerbowa wants to merge 1 commit into
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[AMDGPU] Give 4-cycle gfx1250 WMMA its own co-execution hazard category#3197kerbowa wants to merge 1 commit into
kerbowa wants to merge 1 commit into
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The 4-cycle WMMAs (b0 16x16x64 FP8/BF8 and f8f6f4 with both inputs f4) have a single co-execution slot, so they need fewer wait states than the 8-cycle WMMAs they were previously bucketed with. Add a dedicated category (2 wait states before a dependent WMMA, 1 before a dependent VALU) and map latency 4 to it. On a0 these ops are 8 cycles and keep the category-0 counts, so the distinction falls out of the existing per-stepping latency model.
rampitec
approved these changes
Jul 7, 2026
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The 4-cycle WMMAs (b0 16x16x64 FP8/BF8 and f8f6f4 with both inputs f4) have a single co-execution slot, so they need fewer wait states than the 8-cycle WMMAs they were previously bucketed with. Add a dedicated category (2 wait states before a dependent WMMA, 1 before a dependent VALU) and map latency 4 to it. On a0 these ops are 8 cycles and keep the category-0 counts, so the distinction falls out of the existing per-stepping latency model.