I am an Electronics and Communication Engineering (ECE) undergraduate at S.A. Engineering College (Anna University), Chennai (Expected Graduation: 2028). My engineering focus centers on Embedded Systems, Microcontroller Firmware, and Industrial IoT, with secondary focus on Edge AI and Intelligent Hardware.
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Every featured project represents authentic, auditable engineering work with dedicated visual evidence.
1. LumaGuard
Context-Aware Micro-Workspace Hazard & Proximity Guard
Target: Arduino Nano (ATmega328P @ 16 MHz, 5V) β’ PlatformIO β’ Embedded C/C++
Maturity Lifecycle:Stage 4: Hardware Bench Tested (Physical Breadboard Prototype)
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Physical Embedded System: Assembled and bench-tested on an 830-point solderless breadboard with the ATmega328P Nano, 0.96" SSD1306 OLED (I2C
0x3C), HC-SR04 ultrasonic transducer, optical IR flame sensor, passive piezo buzzer, and control pushbutton. -
Sensory Arbitration: Non-blocking cooperative scheduler executing bi-level distance hysteresis (
$30.0\text{ cm} \to 33.0\text{ cm}$ hold), temporal optical flame candidate persistence ($250\text{ ms}$ ), and proportional audible urgency modulation ($900\text{ ms} \to 180\text{ ms}$ ). -
Fault Detection & Memory: Detects missing echoes (
NO ECHO/ZONE UNKNOWNafter$800\text{ ms}$ ) and persists hazard counter signatures to internal EEPROM across power cycles. - Deterministic Build: Automated PlatformIO CI build matrix verifying AVR memory constraints (35.6% SRAM, 70.5% Flash).
View Repository & Documentation β
Deterministic Virtual Microcontroller Laboratory for ECE Education
Stack: Next.js 16 β’ TypeScript β’ Zustand β’ Vitest (169 Tests) β’ Supabase β’ Apache-2.0
Live System: embeddedlab-os.vercel.app
Maturity Lifecycle:Stage 3: Software Tested (Browser-based simulator; 169 unit & integration tests passing)
- Register Behavioral Simulator: Models STM32-style microcontroller peripheral registers, including GPIO electrical output states, PWM timer duty/period mathematics, ADC quantization transfer equations, and UART frame transmission.
- Automated Validation: 12-challenge automated student grading engine verified by 17 Vitest test suites (169 unit and integration tests passing in CI).
- Engineering Transparency: Explicitly scoped as an educational browser simulation tool, distinguishing register behavior from physical silicon execution and analog SPICE modeling.
Launch Live Simulator Β |Β View Repository β
Industrial Edge AI & LoRa Strata Early-Warning Telemetry System
Stack: ESP32-S3 Firmware (C++) β’ TinyML β’ Sub-GHz LoRa (IN865) β’ Next.js 16 β’ DGMS CMR 2017
Live Deployment: mineguard-sih26025.vercel.app
Maturity Lifecycle:Stage 2: Implemented in Software (ESP32-S3 firmware & software prototype; physical hardware integration incomplete)
- SIH 2026 Prototype: Software telemetry prototype engineered for Smart India Hackathon 2026 (Problem Statement ID: SIH26025) under the Ministry of Coal / Coal India Limited.
- Firmware Architecture: ESP32-S3 driver implementations for BNO085/MPU6050 and ADS1220 24-bit strain gauge ADC, non-blocking FreeRTOS tasks, and theoretical SX1262 LoRa link budget calculations.
- Edge Intelligence: On-device running MAD/EWMA anomaly scoring with adaptive reporting cadences; benchmark achieves 93.00% recall on 1,000 synthetic geomechanical test vectors.
Launch Live Platform Β |Β View Repository β
Multi-Modal Early-Warning Software Demonstrator for Li-ion Battery Thermal Runaway
Stack: Vite β’ React 19 β’ TypeScript β’ Oxlint β’ WCAG 2.1 AA β’ Apache-2.0
Live Demonstrator: quartzsentry-prototype.vercel.app
Maturity Lifecycle:Stage 2: Implemented in Software (Academic software demonstrator with synthetic telemetry)
- Academic Simulation Demonstrator: Software simulation platform modeling early-precursor thermal runaway stages in 16-cell Li-ion battery modules.
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Multi-Modal Sensory Modeling: Mathematical representations of Electrochemical Impedance Spectroscopy (EIS Nyquist drift), ultrasonic acoustic cavitation, off-gas emissions (
$H_2$ / VOCs), and thermodynamic runaway boundaries. - Accessibility & Ethics: WCAG 2.1 AA compliance (6.16:1 text contrast) with prominent disclaimers establishing that telemetry is synthetic with no physical battery pack or certified protection hardware.
Launch Live Demonstrator Β |Β View Repository β
5. CLASSY_CS
Auditable Academic Evaluation, GPA/CGPA & Admissions Planning Platform
Stack: React 19 β’ TypeScript β’ Vite β’ Tailwind CSS v4 β’ Vitest (31 Tests) β’ jsPDF β’ MIT
Maturity Lifecycle:Stage 3: Software Tested (31 unit tests passing)
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Deterministic Evaluation Engine: Computes Anna University 10-point GPA/CGPA credit-weighted evaluations with official Tamil Nadu Engineering Admissions (TNEA) 200-point reduced formulas:
$\text{Cutoff} = M + \frac{P}{2} + \frac{C}{2}$ . - Export & Type Safety: High-resolution client-side PDF/CSV transcript generation and national entrance exam eligibility rulesets (JEE Main, JEE Advanced, NEET UG) verified by 31 Vitest unit tests.
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Civic Problem Verification & Startup Opportunity Ecosystem
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Modern Desktop Task & Productivity Skin
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My firmware development adheres to real-time embedded safety and deterministic execution principles:
- Low-Level Hardware Interfaces: Direct register configuration, ADC sampling calibration, volatile qualifiers, bounded timing loops, and hardware watchdog timer (WDT) refresh cycles.
- Bus Protocols: Hardware I2C (address arbitration, clock stretching, bus recovery), SPI (clock phase/polarity modes), UART (frame buffering, ring buffers), and LoRa sub-GHz packet structures.
- Noise Mitigation: Temporal persistence filtering, moving average filters, and bi-level hysteresis thresholds to eliminate contact bounce and sensor chatter.
Bridging physical sensor instrumentation with embedded machine learning:
- Constrained Anomaly Scoring: Running Median Absolute Deviation (MAD), Exponentially Weighted Moving Average (EWMA), and Robust Z-score algorithms for low-memory microcontrollers.
- Adaptive Telemetry: Dynamic reporting frequency scaling (reducing radio duty cycle during quiescent conditions; escalating packet rate during rapid sensor drift).
- Geotechnical & Battery Research: Physical link budget formulation, InSAR geospatial alignment, and multi-spectral early fault precursor identification.
AWS credentials earned through proctored examinations. Public verification links are provided below; raw AWS validation identifiers are intentionally not published in this README.
| Domain | Competencies & Verified Toolchains |
|---|---|
| Microcontrollers & Silicon | Arduino Nano (ATmega328P @ 16 MHz), ESP32-S3 (Xtensa dual-core), STM32 / ARM Cortex-M architecture, Solderless breadboard prototyping, Voltage domain matching (3.3V / 5V) |
| Firmware & Low-Level C/C++ | PlatformIO, Arduino framework, Direct register access, State machines, Non-blocking cooperative schedulers, Interrupt handlers (ISRs), Watchdog timers (WDT), EEPROM |
| Bus Protocols & RF | Hardware I2C (`0x3C`), SPI (CPOL/CPHA), UART ring buffers, PWM timers, Sub-GHz LoRa (SX1262 / IN865 band), LoRaWAN link budgets |
| Edge AI & Signal Processing | Running Median Absolute Deviation (MAD), Exponentially Weighted Moving Average (EWMA), Robust Z-score rate-of-change, Sensor fusion, Scikit-learn |
| Software Platforms & Web | TypeScript, React 19, Next.js 16 (App Router), Express.js, Zustand, Supabase (PostgreSQL, Row Level Security) |
| DevSecOps & Testing Quality | GitHub Actions CI/CD (Node 26 LTS), PlatformIO CI matrix, Vitest, Jest, Oxlint, ESLint, WCAG 2.1 AA accessibility standards |
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Live technical roadmaps, issue backlogs, and hardware validation tracking:
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| Profile | Channel / Identifier | Status |
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| linkedin.com/in/ron-rex | Verified | |
| Credly Profile | credly.com/users/ronaldrex | Verified (4 AWS Badges) |
| AWS Skill Builder | skillsprofile.skillbuilder.aws/user/ron | Verified |
| GitHub Collaboration | @RONALD-REX-7 | Active |
Crafted with engineering precision β’ Designed with Lavender Cyber-Engineering aesthetic β’ Zero-Fabrication verified








