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Artix7-Delta-Sigma-Decimation-Filter
Artix7-Delta-Sigma-Decimation-Filter PublicA synthesizable, multi-rate 1-Bit Delta-Sigma to 36-Bit CIC Decimation Filter implemented in Verilog and verified on a Xilinx Artix-7 (Basys 3) FPGA.
Verilog 1
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rfid-smart-door-lock
rfid-smart-door-lock PublicArduino-based RFID Smart Door Lock with LCD Interface, Servo Locking Mechanism, Auto-Lock Security, and Failed Attempt Lockout.
C++
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