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University of Siegen
- Siegen, Germany
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06:47
(UTC +02:00)
Popular repositories Loading
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Implementation-of-DoorBell-on-Zynq-7000-
Implementation-of-DoorBell-on-Zynq-7000- PublicA digital design project that simulates a doorbell system using VHDL. The bell activates only when the power switch and the button are pressed ('1'). This project was developed to practice behavior…
VHDL 3
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Implementation-of-AND-gate-on-Zynq-7000
Implementation-of-AND-gate-on-Zynq-7000 PublicA digital logic project implemented in VHDL to simulate and deploy an AND gate on an FPGA. The output goes high ('1') only when both inputs are high. This project was designed to reinforce understa…
VHDL 2
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Implementation-of-OR-Gate-on-Zynq-7000-
Implementation-of-OR-Gate-on-Zynq-7000- PublicA digital logic design in VHDL that simulates and implements an OR gate on an FPGA. The output is high ('1') when at least one of the inputs is high. This project was created to practice basic comb…
VHDL 2
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Memristor-based-LSTM-neuromorphic-review
Memristor-based-LSTM-neuromorphic-review PublicThis repository contains a detailed academic literature review on memristor-based Long Short-Term Memory (LSTM) neuromorphic circuits.
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Healthcare-Monitoring-System-using-NodeMCU
Healthcare-Monitoring-System-using-NodeMCU PublicA embedded system prototype for acquiring and remotely monitoring patient vitals including heart rate, blood oxygen saturation (SpO₂), and temperature
C++ 1
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Silicon-Carbide-Amplifiers-Literature-Review
Silicon-Carbide-Amplifiers-Literature-Review PublicThis repository contains a detailed literature review on **Silicon Carbide (SiC) Amplifiers**, with a specific focus on their structure, applications, challenges, and future scope in high-temperatu…
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