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MIPS32-5-Stage-Pipeline
MIPS32-5-Stage-Pipeline PublicA 32-bit 5-stage pipelined MIPS processor implemented in Verilog HDL. Features include a two-phase non-overlapping clock system, hazard mitigation, and successful verification through Factorial and…
Verilog
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CampusConnect
CampusConnect PublicA full-stack MERN campus community platform for student marketplace, academic resources, events, Lost & Found, and messaging.
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