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Hold DMA upsizer output under backpressure #20

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93f4f5a
Hold DMA upsizer output under backpressure
flaviens Aug 14, 2026
5197cfa
Guard 8-bit upsizer buffer index
flaviens Aug 14, 2026
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40 changes: 25 additions & 15 deletions prj/stream_app/rtl/rtl/rp_gpio/gpio_dma_s2mm_upsize.v
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Original file line number Diff line number Diff line change
Expand Up @@ -21,14 +21,22 @@ module gpio_dma_s2mm_upsize
);

localparam MUX_MAX = AXI_DATA_BITS/AXIS_DATA_BITS;
localparam [1:0] MUX_LAST = MUX_MAX[1:0]-1'b1;

reg [1:0] mux_sel;
reg [6:0] xfer_cnt;
wire [6:0] req_len;
reg tlast;
genvar i;

assign s_axis_tready = 1'b1;
wire input_transfer;
wire output_transfer;
wire word_complete;

assign s_axis_tready = ~m_axis_tvalid | m_axis_tready;
assign input_transfer = s_axis_tvalid & s_axis_tready;
assign output_transfer = m_axis_tvalid & m_axis_tready;
assign word_complete = input_transfer &
((mux_sel == MUX_LAST) | s_axis_tlast);
assign req_len = xfer_cnt+1;

////////////////////////////////////////////////////////////
Expand All @@ -41,7 +49,7 @@ begin
if (rst == 1) begin
xfer_cnt <= 0;
end else begin
if ((m_axis_tvalid == 1) && (m_axis_tready == 1)) begin
if (output_transfer) begin
if (xfer_cnt == AXI_BURST_LEN-1) begin
xfer_cnt <= 0;
end else begin
Expand Down Expand Up @@ -72,7 +80,7 @@ begin
if (rst == 1) begin
req_we <= 0;
end else begin
if (((m_axis_tvalid == 1) && (m_axis_tready == 1) && ((tlast == 1) || (xfer_cnt == AXI_BURST_LEN-1)))) begin
if (output_transfer && ((tlast == 1) || (xfer_cnt == AXI_BURST_LEN-1))) begin
req_we <= 1;
end else begin
req_we <= 0;
Expand All @@ -91,8 +99,8 @@ begin
if (rst == 1) begin
mux_sel <= 0;
end else begin
if ((s_axis_tvalid == 1) && (s_axis_tready == 1)) begin
if (mux_sel == MUX_MAX-1) begin
if (input_transfer) begin
if ((mux_sel == MUX_LAST) || s_axis_tlast) begin
mux_sel <= 0;
end else begin
mux_sel <= mux_sel + 1;
Expand All @@ -110,7 +118,7 @@ generate
for (i=0; i<MUX_MAX; i=i+1) begin : gen_data
always @(posedge clk)
begin
if (mux_sel == i) begin
if ((mux_sel == i) && input_transfer) begin
m_axis_tdata[i*AXIS_DATA_BITS +: AXIS_DATA_BITS] <= s_axis_tdata;
end
end
Expand All @@ -127,10 +135,10 @@ always @(posedge clk)
begin
if (rst == 1) begin
m_axis_tvalid <= 0;
end else begin
if (((mux_sel == MUX_MAX-1) || (s_axis_tlast == 1)) && (s_axis_tvalid == 1) && (s_axis_tready == 1)) begin
end else begin
if (word_complete) begin
m_axis_tvalid <= 1;
end else begin
end else if (output_transfer) begin
m_axis_tvalid <= 0;
end
end
Expand All @@ -145,11 +153,13 @@ always @(posedge clk)
begin
if (rst == 1) begin
tlast <= 0;
end else begin
if ((s_axis_tlast == 1) && (s_axis_tvalid == 1) && (s_axis_tready == 1)) begin
tlast <= 1;
end
end else begin
if (word_complete) begin
tlast <= s_axis_tlast;
end else if (output_transfer) begin
tlast <= 0;
end
end
end

endmodule
endmodule
45 changes: 29 additions & 16 deletions prj/stream_app/rtl/rtl/rp_oscilloscope/rp_dma_s2mm_upsize.v
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Original file line number Diff line number Diff line change
Expand Up @@ -28,8 +28,15 @@ reg tlast;

reg [8-1:0] upsize_buf [8-1:0];
reg [3-1:0] mux_sel;

assign s_axis_tready = 1'b1;
wire input_transfer;
wire output_transfer;
wire word_complete;

assign s_axis_tready = ~m_axis_tvalid | m_axis_tready;
assign input_transfer = s_axis_tvalid & s_axis_tready;
assign output_transfer = m_axis_tvalid & m_axis_tready;
assign word_complete = input_transfer &
((&(mux_sel | {2'b0, ~use_8bit})) | s_axis_tlast);
assign req_len = xfer_cnt+1;
assign upsize_lvl = mux_sel;

Expand All @@ -52,7 +59,7 @@ begin
if (rst == 1) begin
xfer_cnt <= 0;
end else begin
if ((m_axis_tvalid == 1) && (m_axis_tready == 1)) begin
if (output_transfer) begin
if (xfer_cnt == AXI_BURST_LEN-1) begin
xfer_cnt <= 0;
end else begin
Expand Down Expand Up @@ -83,7 +90,7 @@ begin
if (rst == 1) begin
req_we <= 0;
end else begin
if (((m_axis_tvalid == 1) && (m_axis_tready == 1) && ((tlast == 1) || (xfer_cnt == AXI_BURST_LEN-1)))) begin
if (output_transfer && ((tlast == 1) || (xfer_cnt == AXI_BURST_LEN-1))) begin
req_we <= 1;
end else begin
req_we <= 0;
Expand All @@ -102,8 +109,8 @@ begin
if (rst == 1) begin
mux_sel <= 0;
end else begin
if ((s_axis_tvalid == 1) && (s_axis_tready == 1)) begin
if (&(mux_sel | {2'b0, ~use_8bit})) begin
if (input_transfer) begin
if ((&(mux_sel | {2'b0, ~use_8bit})) || s_axis_tlast) begin
mux_sel <= 0;
end else begin
mux_sel <= mux_sel + {1'b0, ~use_8bit, use_8bit};
Expand All @@ -119,8 +126,12 @@ end

always @(posedge clk)
begin
upsize_buf[mux_sel ] <= (s_axis_tdata[16-1:8] & {8{ use_8bit}}) | (s_axis_tdata[8-1:0] & {8{~use_8bit}});
upsize_buf[mux_sel+1] <= (s_axis_tdata[16-1:8] & {8{~use_8bit}}) | (upsize_buf[mux_sel+1] & {8{ use_8bit}});
if (input_transfer) begin
upsize_buf[mux_sel ] <= (s_axis_tdata[16-1:8] & {8{ use_8bit}}) | (s_axis_tdata[8-1:0] & {8{~use_8bit}});
if (!use_8bit) begin
upsize_buf[mux_sel+1] <= s_axis_tdata[16-1:8];
end
end
end

////////////////////////////////////////////////////////////
Expand All @@ -133,10 +144,10 @@ always @(posedge clk)
begin
if (rst == 1) begin
m_axis_tvalid <= 0;
end else begin
if (( (&(mux_sel | {2'b0, ~use_8bit})) || (s_axis_tlast == 1)) && (s_axis_tvalid == 1) && (s_axis_tready == 1)) begin
end else begin
if (word_complete) begin
m_axis_tvalid <= 1;
end else begin
end else if (output_transfer) begin
m_axis_tvalid <= 0;
end
end
Expand All @@ -151,11 +162,13 @@ always @(posedge clk)
begin
if (rst == 1) begin
tlast <= 0;
end else begin
if ((s_axis_tlast == 1) && (s_axis_tvalid == 1) && (s_axis_tready == 1)) begin
tlast <= 1;
end
end else begin
if (word_complete) begin
tlast <= s_axis_tlast;
end else if (output_transfer) begin
tlast <= 0;
end
end
end

endmodule
endmodule
40 changes: 25 additions & 15 deletions prj/stream_app/rtl/rtl_250/rp_gpio/gpio_dma_s2mm_upsize.v
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -21,14 +21,22 @@ module gpio_dma_s2mm_upsize
);

localparam MUX_MAX = AXI_DATA_BITS/AXIS_DATA_BITS;
localparam [1:0] MUX_LAST = MUX_MAX[1:0]-1'b1;

reg [1:0] mux_sel;
reg [6:0] xfer_cnt;
wire [6:0] req_len;
reg tlast;
genvar i;

assign s_axis_tready = 1'b1;
wire input_transfer;
wire output_transfer;
wire word_complete;

assign s_axis_tready = ~m_axis_tvalid | m_axis_tready;
assign input_transfer = s_axis_tvalid & s_axis_tready;
assign output_transfer = m_axis_tvalid & m_axis_tready;
assign word_complete = input_transfer &
((mux_sel == MUX_LAST) | s_axis_tlast);
assign req_len = xfer_cnt+1;

////////////////////////////////////////////////////////////
Expand All @@ -41,7 +49,7 @@ begin
if (rst == 1) begin
xfer_cnt <= 0;
end else begin
if ((m_axis_tvalid == 1) && (m_axis_tready == 1)) begin
if (output_transfer) begin
if (xfer_cnt == AXI_BURST_LEN-1) begin
xfer_cnt <= 0;
end else begin
Expand Down Expand Up @@ -72,7 +80,7 @@ begin
if (rst == 1) begin
req_we <= 0;
end else begin
if (((m_axis_tvalid == 1) && (m_axis_tready == 1) && ((tlast == 1) || (xfer_cnt == AXI_BURST_LEN-1)))) begin
if (output_transfer && ((tlast == 1) || (xfer_cnt == AXI_BURST_LEN-1))) begin
req_we <= 1;
end else begin
req_we <= 0;
Expand All @@ -91,8 +99,8 @@ begin
if (rst == 1) begin
mux_sel <= 0;
end else begin
if ((s_axis_tvalid == 1) && (s_axis_tready == 1)) begin
if (mux_sel == MUX_MAX-1) begin
if (input_transfer) begin
if ((mux_sel == MUX_LAST) || s_axis_tlast) begin
mux_sel <= 0;
end else begin
mux_sel <= mux_sel + 1;
Expand All @@ -110,7 +118,7 @@ generate
for (i=0; i<MUX_MAX; i=i+1) begin : gen_data
always @(posedge clk)
begin
if (mux_sel == i) begin
if ((mux_sel == i) && input_transfer) begin
m_axis_tdata[i*AXIS_DATA_BITS +: AXIS_DATA_BITS] <= s_axis_tdata;
end
end
Expand All @@ -127,10 +135,10 @@ always @(posedge clk)
begin
if (rst == 1) begin
m_axis_tvalid <= 0;
end else begin
if (((mux_sel == MUX_MAX-1) || (s_axis_tlast == 1)) && (s_axis_tvalid == 1) && (s_axis_tready == 1)) begin
end else begin
if (word_complete) begin
m_axis_tvalid <= 1;
end else begin
end else if (output_transfer) begin
m_axis_tvalid <= 0;
end
end
Expand All @@ -145,11 +153,13 @@ always @(posedge clk)
begin
if (rst == 1) begin
tlast <= 0;
end else begin
if ((s_axis_tlast == 1) && (s_axis_tvalid == 1) && (s_axis_tready == 1)) begin
tlast <= 1;
end
end else begin
if (word_complete) begin
tlast <= s_axis_tlast;
end else if (output_transfer) begin
tlast <= 0;
end
end
end

endmodule
endmodule
45 changes: 29 additions & 16 deletions prj/stream_app/rtl/rtl_250/rp_oscilloscope/rp_dma_s2mm_upsize.v
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -28,8 +28,15 @@ reg tlast;

reg [8-1:0] upsize_buf [8-1:0];
reg [3-1:0] mux_sel;

assign s_axis_tready = 1'b1;
wire input_transfer;
wire output_transfer;
wire word_complete;

assign s_axis_tready = ~m_axis_tvalid | m_axis_tready;
assign input_transfer = s_axis_tvalid & s_axis_tready;
assign output_transfer = m_axis_tvalid & m_axis_tready;
assign word_complete = input_transfer &
((&(mux_sel | {2'b0, ~use_8bit})) | s_axis_tlast);
assign req_len = xfer_cnt+1;
assign upsize_lvl = mux_sel;

Expand All @@ -52,7 +59,7 @@ begin
if (rst == 1) begin
xfer_cnt <= 0;
end else begin
if ((m_axis_tvalid == 1) && (m_axis_tready == 1)) begin
if (output_transfer) begin
if (xfer_cnt == AXI_BURST_LEN-1) begin
xfer_cnt <= 0;
end else begin
Expand Down Expand Up @@ -83,7 +90,7 @@ begin
if (rst == 1) begin
req_we <= 0;
end else begin
if (((m_axis_tvalid == 1) && (m_axis_tready == 1) && ((tlast == 1) || (xfer_cnt == AXI_BURST_LEN-1)))) begin
if (output_transfer && ((tlast == 1) || (xfer_cnt == AXI_BURST_LEN-1))) begin
req_we <= 1;
end else begin
req_we <= 0;
Expand All @@ -102,8 +109,8 @@ begin
if (rst == 1) begin
mux_sel <= 0;
end else begin
if ((s_axis_tvalid == 1) && (s_axis_tready == 1)) begin
if (&(mux_sel | {2'b0, ~use_8bit})) begin
if (input_transfer) begin
if ((&(mux_sel | {2'b0, ~use_8bit})) || s_axis_tlast) begin
mux_sel <= 0;
end else begin
mux_sel <= mux_sel + {1'b0, ~use_8bit, use_8bit};
Expand All @@ -119,8 +126,12 @@ end

always @(posedge clk)
begin
upsize_buf[mux_sel ] <= (s_axis_tdata[16-1:8] & {8{ use_8bit}}) | (s_axis_tdata[8-1:0] & {8{~use_8bit}});
upsize_buf[mux_sel+1] <= (s_axis_tdata[16-1:8] & {8{~use_8bit}}) | (upsize_buf[mux_sel+1] & {8{ use_8bit}});
if (input_transfer) begin
upsize_buf[mux_sel ] <= (s_axis_tdata[16-1:8] & {8{ use_8bit}}) | (s_axis_tdata[8-1:0] & {8{~use_8bit}});
if (!use_8bit) begin
upsize_buf[mux_sel+1] <= s_axis_tdata[16-1:8];
end
end
end

////////////////////////////////////////////////////////////
Expand All @@ -133,10 +144,10 @@ always @(posedge clk)
begin
if (rst == 1) begin
m_axis_tvalid <= 0;
end else begin
if (( (&(mux_sel | {2'b0, ~use_8bit})) || (s_axis_tlast == 1)) && (s_axis_tvalid == 1) && (s_axis_tready == 1)) begin
end else begin
if (word_complete) begin
m_axis_tvalid <= 1;
end else begin
end else if (output_transfer) begin
m_axis_tvalid <= 0;
end
end
Expand All @@ -151,11 +162,13 @@ always @(posedge clk)
begin
if (rst == 1) begin
tlast <= 0;
end else begin
if ((s_axis_tlast == 1) && (s_axis_tvalid == 1) && (s_axis_tready == 1)) begin
tlast <= 1;
end
end else begin
if (word_complete) begin
tlast <= s_axis_tlast;
end else if (output_transfer) begin
tlast <= 0;
end
end
end

endmodule
endmodule
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