This repo contains:
- Original Norsk Data ND-120 CPU Design Documents from 1988. Scanned in 2023
- Modern Logisim and HDL implementation from 2023.
You can read more about this CPU and much more in NDWiki and the official website for Norsk Data
The goal of this repo is to re-create the schematics and create the HDL files so we can program an FPGA to run as the original ND-120 CPU Card.
On the way to the FPGA code, there will be testable Logisim Circuits and Logisim code that can be converted and tested in C++ using Verilator.
Simulation (Verilator, the golden reference):
- Microcode loads, Master Clear executes, CPU self-test runs
(7 of 14 subtests passing - the remaining failures are CPU-core
suspects, proven unrelated to memory parity: see
Verilog/docs/nd120-parity-analysis.md) - OPCOM console works;
INSTRUCTION-Bloads and runs from the Verilog papertape device; DMA bus mastering against the real arbiter - Golden-console and latch-vs-FF regression gates keep it all pinned
FPGA hardware:
- Basys3: OPCOM boots on the board (tag
fpga-opcom-working-basys3); active debug line at 16.67 MHz - Tang Nano 20K: full CPU bitstream with 4 MB SDRAM main memory
(packed 16-bit storage, computed parity -
ND_SDRAM_PACK16), the other 4 MB reserved for the SD disk-image cache; SD/FAT stack proven on hardware (read + write, safety-gated) - Dual toolchain: the Tang builds with the OSS CAD Suite
(yosys/nextpnr, primary) and Gowin EDA (backup) - all clock variants;
nextpnr closes the full 27/54 MHz target with >2x margin
(
Verilog/docs/tang20k-build-flows.md) - Cmod A7-35T: first build ready (BRAM memory, CPU at 27 MHz);
512 KB SRAM main-memory bridge planned
(
Verilog/fpga/cmod-a7-35t/SRAM-BRIDGE-PLAN.md) - Memory-backend speed rules for every board (what meets the no-wait-state
protocol at 40 MHz and what cannot):
Verilog/docs/basys3-memory-speed-validation.md
cd Verilog\sim
make clean
make all # Compiles, runs, and opens GTKWavePrerequisites: Verilator, GTKWave (optional), Windows with PowerShell
See BUILDING.md for detailed build and test instructions.
The minimum requirements to make the CPU work:
| Component | Schematic | HDL | Status |
|---|---|---|---|
| DELILAH CPU Gate Array (CGA) | Completed | Logisim generated Verilog | QA on schematic/Verilog ongoing |
| NEC Decoder Gate Array (DGA) | Completed | Logisim generated Verilog | QA on schematic/Verilog ongoing |
| ND 3202 CPU Board revision D | Completed | Logisim generated Verilog | QA on schematic/Verilog ongoing |
| PAL Chips | All PALASM code has been validated | Verilog and testcode created | QA on Verilog ongoing |
In the CPU Board we will plug in the DELILAH CPU and the Decoder, all PAL chips and several other support chips (74-series, RAM and UART).
Compressed history of the work progress:
| Date | Description |
|---|---|
| 11. March 2023 | Received Design Documentation from Lasse Bockelie |
| 21. August 2023 | Logisim Drawings completed for DGA and DELILAH/CGA |
| 03. December 2023 | Using Logisim drawings to start generate Verilog files for DGA and CGA |
| 12. December 2023 | Starting to consolidate all information about PAL chips (PNG for PALASM code, OCR to TXT and write Verilog version of PAL code) |
| 26. December 2023 | Logisim drawings of CPU Board 3202D completed |
| 27. December 2023 | Using Logisim drawings to start generate Verilog files for CPU Board 3202D |
| 11. January 2024 | Most PALASM code has been ported to Verilog |
| January-June 2024 | Adding support chips, refactoring and bugfixing. Adding tests and test results |
| June-November 2024 | No work done |
| 9. November 2024 | Starting up again after a long break. Cleaning up code, refactoring and testing. Connecting everything together. |
| 20. November 2024 | Verilator - Microcode is loaded from ROM to DRAM. MACL microcode starts but fail on STACK operations, and fails on COND operations. |
| 13. December 2024 | Verilator - Microcode MACL starts, CPU test code runs. OPCOM is initialized and communication over UART works. |
| 29. Januar 2025 | Verilator - Testprogram 'INSTRUCTION-B.BPUN' (204384B 83.11.01) loads and starts. 7 out of 14 tests succeed. |
| 22. Mars 2025 | Verilator & C++ - Interface with ND BUS via BIF module to C connector. Added support for Papertape reader and Floppy PIO written in C++ |
| 1. June 2025 | Reverse engineered the ROM chips for the panel controller's with help of Ghidra and Claude.AI |
| 7. July 2026 | OPCOM boots on Basys3 hardware (tag fpga-opcom-working-basys3); FF-mode clock architecture fixes |
| 11. July 2026 | SD/FAT stack proven on Tang Nano 20K hardware (read+write); microcode analysis proves the self-test never touches memory parity -> packed 16-bit SDRAM storage (ND_SDRAM_PACK16): CPU keeps 4 MB, 4 MB freed for the disk cache |
| 12. July 2026 | Dual-toolchain Tang builds: OSS CAD Suite (yosys/nextpnr) primary, Gowin EDA backup; nextpnr closes the full 27/54 MHz clock target with >2x margin |
| 13. July 2026 | Basys3 SD-Pmod port; memory-backend speed validation vs the no-wait-state protocol for every board; Cmod A7-35T activated (first 27 MHz BRAM build + SRAM bridge plan) |
All the design documents are in the Design Documents folder.
Functional Description, Instruction set, Microprogramming guide and more are in the NorskData-Doc folder.
The Microcode dump is from a ND-120 3202 CPU Board is Version 14/L The source code is also for the L version.
The ND-120/CX CPU Board has an on-board MC68705-U3 CPU.
The physical front panel also has an MC68705 CPU, however this chip is not identical to the on on the 3202D CPU Board - its an MC68705-P3 with fewer I/O pins.
The MC68705 is an MC 6805 8-bit CPU with on-chip RAM, I/O and Timer. Motorola 68HC05
- P3 version = 28 pins, 2x 8 bits I/O ports, 1x 4 bit I/O port
- U3 version = 40 pins, 4x 8 bits I/O ports
We have a ROM dumps from both the MC68705-U3 chip (from the 3202D CPU Board) and the MC68705-P3 (from an ND-5000C panel controller).
Big thanks to Matthieu Benoit for reading the data out of the chips
Reverse engineering has been done using the free SRE tool GHIDRA from NSA.
All the Logisim files are stored in the Logisim folder
You need to install the Logisim-Evolution design tool from Logisim Evolution Repository
The Logisim diagrams has been drawn with Version 3.8.0
The project targets several FPGA boards, each with its own folder of build scripts, pin constraints, vendor documentation and bring-up plans under Verilog/fpga/.
For the current per-board FPGA status, target line-up and priority order, see Verilog/fpga/README.md.
Most Verilog files are generated from the Logisim drawings, using Logisim-Evolution FPGA tools.
All the Verilog files are stored in the Verilog folder
To test the Verilog code using Verilator you need to install the Verilator tool
| Document | Description |
|---|---|
| BUILDING.md | Build instructions, testing, and troubleshooting |
| DEVELOPMENT.md | Project history, architecture, and contribution guide |
| HARDWARE.md | Hardware specifications and component details |
- Lasse Bockelie - Provided original 1988 design documentation
- Matthieu Benoit - ROM chip reading and data extraction
- NDWiki Community - Comprehensive ND-120 documentation
- GHIDRA Team - Reverse engineering tools
- Claude.AI - Analysis assistance