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1. Synopsys-VLSI-flow-Learning-RTL2GDS Synopsys-VLSI-flow-Learning-RTL2GDS Public

   This repository documents a comprehensive hands-on learning journey through the Synopsys Digital Design Flow, covering the complete RTL-to-GDSII process—from RTL synthesis to static timing analysis…

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2. single-stage-pipeline-register single-stage-pipeline-register Public

   8-bit single stage pipeline register in SystemVerilog (Vivado)

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3. 7T-SRAM-Cell-Cadence-Virtuoso-90nm-pdk-file- 7T-SRAM-Cell-Cadence-Virtuoso-90nm-pdk-file- Public

   Design and analysis of a 7T SRAM cell using Cadence Virtuoso in 90 nm CMOS technology.

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4. Digital-Logic-Gates-Verilog-Cadence Digital-Logic-Gates-Verilog-Cadence Public

   Implementation and simulation of fundamental digital logic gates using Verilog HDL in Cadence with functional waveforms and testbenches.