Architecture-independent exploration of numerical representations at 8 bits and below for edge CNN inference. The project compares complete numerical architectures—weight format, activation format, accumulator, scaling, signedness, MAC semantics, and generic hardware implementation—under measured quality, area, energy, and throughput.
This repository covers the public precision-exploration study only. It does not contain the MANT ISA, compiler, mapping, simulator, tile, RTL, interconnect, or chip implementation. The only MANT-facing output is a versioned candidate package that can be imported by a separate private repository after the public Pareto study.
The two HTML files in docs/source/ are preserved planning inputs. Their statements are documented as proposals, source-stated baselines, or evidence-gated decisions; they are not silently treated as new user instructions. Where the earlier plan and later roadmap differ, the later roadmap refinement is called out explicitly.
Which sub-8-bit numerical representation gives the best accuracy–area–energy–throughput trade-off for real edge CNN inference under actual silicon constraints?
The central hypothesis is that the smallest multiplier will not necessarily produce the best complete accelerator. Accumulator width, scaling and conversion, memory density, metadata, communication, control, and realistic switching activity can reorder the arithmetic-only Pareto frontier.
- FP32/FP16 reference reproduction and fixed ImageNet/COCO workload manifests.
- Datatype manifests and a high-precision arithmetic oracle.
- Controlled Experiment A and optimized Experiment B PTQ.
- Bit-exact reference, C++, and CUDA inference.
- Paired statistical screening, conservative promotion, and full validation.
- Generic arithmetic, MAC/FPU, scaling/conversion, memory, and PE/tile RTL DSE.
- ICS55 synthesis/P&R as the primary hardware flow, with optional cross-check flows.
- Generic end-to-end, confidence-aware Pareto analysis.
- Versioned export of approximately 5–10 Pareto and guard candidates.
- Public research/reproduction packaging.
- MANT-specific ISA and instruction encoding.
- MANT golden model, mapping, compiler, and cycle simulator.
- MANT tile/uFPU, memory organization, interconnect, RTL, floorplan, and whole-chip choice.
- Retraining or quantization-aware training; the supplied plan uses PTQ only.
- Approximate arithmetic in the primary study; it is only an optional later branch.
docs/analysis/document-synthesis.md— reconciled analysis of the two inputs.docs/architecture/repository-layout.md— directory ownership and dependency rules.docs/contracts/README.md— Phase 0 contract set.docs/methodology/README.md— complete numerical, statistical, and hardware methods.docs/roadmap/README.md— work packages, phases, dependencies, and scope boundary.docs/decisions/decision-register.md— F1–F8 and D1–D14 with evidence requirements.docs/publications/README.md— public paper and release plan.
| Path | Purpose |
|---|---|
docs/ |
Sources, analysis, contracts, decisions, methodology, roadmap, and publication plan |
public/ |
Architecture-independent numerical software and generic hardware study |
data/ |
Tracked dataset/checkpoint identities and fixed sample lists; raw datasets remain external |
artifacts/ |
Reproducible heavyweight outputs addressed by experiment/configuration identity |
cache/ |
Disposable acceleration data |
results/ |
Run databases, summaries, plots, tables, and exported candidate packages |
tests/ |
Primitive conformance through full-pipeline regression |
tools/ |
Thin setup, run, and report entry points |
Phases 0–7 are the core public study and are implemented here. Public research synthesis and release tasks from Phase 11 also belong here. Roadmap Phases 8–10 and the MANT engineering tasks in Phase 11 are documented for handoff context only and must execute in a separate private MANT repository.
Phase 0 completed on 2026-09-04. Phase 1 completed and was reverified on 2026-09-08 after correcting the audit findings, with frozen workloads and datasets, 25 accepted datatype manifests, a validated oracle and regenerated exhaustive conformance tables, a tested experiment registry, reproducible FP32 baselines, and a public ICsprout55 RVT synthesis/STA pilot. Phase 2 completed on 2026-09-11: exact reference/C++/CUDA execution, all 25-format conformance, native-image checks across four models, all calibration artifacts and frozen baseline predictions, and generic hardware pilots are verified. D2 is accepted for the measured FP6/INT8 GEMM scope; D3 keeps EfficientNet optional. The source-frozen results/summaries/phase2-final-verification.json reports completion with no remaining gates. See docs/roadmap/phases/phase-02-remaining-work.md for the completion checklist and docs/architecture/exact-engine.md for execution commands and evidence limits.
Phase 3 status verified on 2026-09-16: all 100 configurations have calibration
and encoded graphs; paired FP32 baselines, resumable execution, statistics,
layer diagnostics and hardware/storage priors are implemented. Five configurations
passed eight-image C++/CUDA acceptance: ResNet18 INT8/6/5/4 and MobileNetV2 INT8.
The first full 1k screen, ResNet18 INT8, is complete: Top-1 is 68.4% versus
FP32 70.1%, with an UNCERTAIN retention label. MobileNetV2 INT8 is screening.
Additional CPU pilots, eight classifier one-operation studies, detector and
logarithmic-residual diagnoses, and a separate native BFP6 diagnostic are retained.
The other 99 full screens, remaining acceptance gates and D4 review are unfinished.
See the
Phase 3 execution guide and
remaining-work checklist.