Impl/topic28

.github/workflows/ci.yml

@@ -107,6 +107,15 @@ jobs:
         run: |
           python3.12 -m pytest tests/test_pr37_regression.py -v --tb=short
 
+      - name: Run topic28 extended-isel regressions
+        run: |
+          python3.12 -m pytest \
+            tests/test_extended_isel_cli.py \
+            tests/test_inst_select_ext.py \
+            tests/test_riscv_encoder_fd.py \
+            tests/test_topic28_extended_isel_case_report.py \
+            -v --tb=short
+
       - name: Generate test visualization page
         if: github.ref == 'refs/heads/main'
         run: |
@@ -218,6 +227,14 @@ jobs:
             --json benchmark_reports/const_merge_report.json \
             --markdown benchmark_reports/const_merge_report.md
 
+      # ── 3.1.3 课题28：扩展指令选择 case 报告（A/B + 编码器门禁） ───────
+      - name: Topic 28 extended instruction-selection case report
+        run: |
+          mkdir -p benchmark_reports
+          python3.12 benchmarks/run_topic28_extended_isel_case.py \
+            --json benchmark_reports/extended_isel_report.json \
+            --markdown benchmark_reports/extended_isel_report.md
+
       # ── 3.2 DSL 用例编译 + 模拟基准 ────────────────────────────────────
       - name: DSL case compilation benchmarks
         run: |
@@ -363,6 +380,9 @@ jobs:
           if [ -f benchmark_reports/const_merge_report.md ]; then
             cat benchmark_reports/const_merge_report.md >> $GITHUB_STEP_SUMMARY
           fi
+          if [ -f benchmark_reports/extended_isel_report.md ]; then
+            cat benchmark_reports/extended_isel_report.md >> $GITHUB_STEP_SUMMARY
+          fi
           echo "" >> $GITHUB_STEP_SUMMARY
           if [ -f benchmark_reports/github_summary.md ]; then
             cat benchmark_reports/github_summary.md >> $GITHUB_STEP_SUMMARY

benchmarks/cases/topic28_extended_isel_feature.dsl

@@ -0,0 +1,20 @@
+# Topic 28 extended instruction-selection feature case (deterministic).
+#
+# The stock DSL frontend (scratchv/frontend/dsl_parser.py) exposes a closed op
+# table: add/sub/mul/div/neg/exp/relu/gelu/dot/matmul/softmax/maxpool.  The
+# Topic 28 opcodes (sqrt/min/max/abs/idiv/rem/mod and the float64 family) have
+# no DSL syntax, so this file drives the CompilerDriver A/B wiring check while
+# the extended-only instruction shapes are probed at IR level by
+# benchmarks/run_topic28_extended_isel_case.py (see its honesty note).
+#
+# Loop trip count 0..3 leaves acc = 6, sq = 36, bias = relu(36) = 36.
+# neg_acc = -6; total = 36 - (-6) = 42; res = 42 / 6 = 7.
+for i = 0, 4
+  acc = add(i, i)
+  sq = mul(acc, acc)
+  bias = relu(sq)
+endfor
+neg_acc = neg(acc)
+total = sub(bias, neg_acc)
+res = div(total, acc)
+return res