Impl/topic29

.github/workflows/ci.yml

@@ -107,6 +107,15 @@ jobs:
         run: |
           python3.12 -m pytest tests/test_pr37_regression.py -v --tb=short
 
+      - name: Run topic29 SIMD-vectorize regressions
+        run: |
+          python3.12 -m pytest \
+            tests/test_vectorize.py \
+            tests/test_vector_lowering.py \
+            tests/test_vector_encoder.py \
+            tests/test_topic29_vectorize_case_report.py \
+            -v --tb=short
+
       - name: Generate test visualization page
         if: github.ref == 'refs/heads/main'
         run: |
@@ -218,6 +227,14 @@ jobs:
             --json benchmark_reports/const_merge_report.json \
             --markdown benchmark_reports/const_merge_report.md
 
+      # ── 3.1.2 课题29：SIMD 向量化 case 报告（A/B + RV32 执行等价） ─────
+      - name: Topic 29 SIMD vectorize case report
+        run: |
+          mkdir -p benchmark_reports
+          python3.12 benchmarks/run_topic29_vectorize_case.py \
+            --json benchmark_reports/vectorize_report.json \
+            --markdown benchmark_reports/vectorize_report.md
+
       # ── 3.2 DSL 用例编译 + 模拟基准 ────────────────────────────────────
       - name: DSL case compilation benchmarks
         run: |
@@ -363,6 +380,9 @@ jobs:
           if [ -f benchmark_reports/const_merge_report.md ]; then
             cat benchmark_reports/const_merge_report.md >> $GITHUB_STEP_SUMMARY
           fi
+          if [ -f benchmark_reports/vectorize_report.md ]; then
+            cat benchmark_reports/vectorize_report.md >> $GITHUB_STEP_SUMMARY
+          fi
           echo "" >> $GITHUB_STEP_SUMMARY
           if [ -f benchmark_reports/github_summary.md ]; then
             cat benchmark_reports/github_summary.md >> $GITHUB_STEP_SUMMARY

benchmarks/cases/topic29_vectorize_feature.dsl

@@ -0,0 +1,13 @@
+# SIMD vectorize feature case (Topic 29, phase 1).
+#
+# Scalar shape mirrored by the report's vectorizable IR case:
+#   out[i] = relu(a[i] + a[i])  for i in [0, 16)
+# The phase-1 DSL grammar has no array load/store syntax, so the report
+# builds the canonical element-addressing IR (design doc appendix 5.1)
+# and compiles it through CompilerDriver; this file is still read and
+# validated by every driver call and compiled off/on in the wiring check.
+for i = 0, 16
+  t = add(x, x)
+  y = relu(t)
+endfor
+return y