SHA1 Hardware Accelerator — Intel MAX 10 DECA

Overview

A hybrid CPU+FPGA SHA1 accelerator on the Arrow DECA board (Intel MAX 10 — 10M50DAF484C6GES). The Nios II soft-core CPU handles message padding and Avalon bus communication, while a dedicated SystemVerilog SHA1 engine performs the 80-round hash computation in hardware (~146 clock cycles per 512-bit block).

Architecture

Nios II CPU (C software)
    |  1. Pad message into 16 x 32-bit words
    |  2. Write W[0..15] to MSG registers
    |  3. Write CTRL = START
    v
sha1_avalon.sv  (Avalon MM Slave)
    |  Expands W[16..79] + runs 80 compress rounds
    v
sha1_core.sv  (Pure SHA1 FSM)
    |  Sets STATUS.done when complete
    v
Nios II reads H0..H4  =>  160-bit hash result

Repository Structure

SHA1_Implementation/
|-- fsoc_sha_top.sv             Top-level FPGA design
|-- fsoc_sha_top.qpf            Quartus project file
|-- fsoc_sha_top.qsf            Quartus settings + pin assignments
|-- base_sys.qsys               Platform Designer system
|-- base_sys.sopcinfo           Generated SOPC info (for BSP)
|-- sha1_core.sv                SHA1 computation FSM (80 rounds)
|-- sha1_avalon.sv              Avalon MM slave wrapper
|-- sha1_avalon_hw.tcl          Platform Designer component TCL
|-- avalon_eval_core_0.sv       Eval core 0 (read-wait 0)
|-- avalon_eval_core_1.sv       Eval core 1 (read-wait 1)
|-- avalon_eval_core_2.sv       Eval core 2 (read+write wait)
|-- avalon_eval_core_0_hw.tcl
|-- avalon_eval_core_1_hw.tcl
|-- avalon_eval_core_2_hw.tcl
+-- software/
    |-- sha1_app/
    |   +-- main.c              Nios II hybrid SHA1 test app
    +-- sha1_app_bsp/
        +-- settings.bsp        BSP configuration

Hardware Platform

Item	Details
Board	Arrow DECA
Device	Intel MAX 10 - 10M50DAF484C6GES
Tool	Quartus Prime Lite 18.1
CPU	Nios II/f @ 50 MHz
Memory	40 KB on-chip SRAM
Interface	Avalon Memory-Mapped Slave

SHA1 Register Map

Address	Register	Access	Description
0x00	CTRL	W	bit0=start, bit1=reset
0x04	STATUS	R	bit0=busy, bit1=done
0x08	MSG[0]	W	Padded message word 0
...	...	W	...
0x44	MSG[15]	W	Padded message word 15
0x48	H0_OUT	R	Hash result word 0
0x4C	H1_OUT	R	Hash result word 1
0x50	H2_OUT	R	Hash result word 2
0x54	H3_OUT	R	Hash result word 3
0x58	H4_OUT	R	Hash result word 4

Resource Utilisation

Resource	Used	Available	Percent
Logic Elements	10,629	49,760	21%
Registers	5,877	-	-
Memory bits	383,360	1,677,312	23%
9-bit Multipliers	6	288	2%

Test Vectors (RFC 3174 Verified)

Input	SHA1 Hash
"abc"	a9993e36 4706816a ba3e2571 7850c26c 9cd0d89d
""	da39a3ee 5e6b4b0d 3255bfef 95601890 afd80709
"Hello DECA"	fddf5061 5bac8c16 29ebbe86 3f03c9d0 b9166ff4

How to Build

Hardware

1. Open fsoc_sha_top.qpf in Quartus Prime Lite 18.1
2. Processing -> Start Compilation (Ctrl+L)
3. Tools -> Programmer -> load fsoc_sha_top.sof -> Start

Software (Nios II Eclipse SBT)

1. Right-click sha1_app_bsp -> Nios II -> Generate BSP
2. Right-click sha1_app     -> Build Project
3. Right-click sha1_app     -> Run As -> Nios II Hardware
4. Check Nios II Console tab for hash output

Author

Shreyanka Kumbar