Micro-Architecture L1 Cache Simulator

A C simulator modeling a Direct-Mapped L1 Instruction/Data Cache pipeline. Demonstrates address translation (Offset, Index, Tag), valid bit status flags, and hit/miss evaluation.

Key Concepts

• Direct Mapping: Maps memory addresses directly to cache index locations using modular arithmetic.
• Tag Verification: Checks valid bit and address tags to classify Cache Hits vs. Cache Misses.
• Performance Evaluation: Simulates memory access pipelines to evaluate spatial and temporal locality.

Compilation & Run

gcc cache_sim.c -o cache_sim
./cache_sim