Skip to content

Home

Jump to bottom
Erik Piehl edited this page Apr 22, 2016 · 15 revisions

Welcome to the fpga99 wiki!

This wiki has currently a few pages. I recommend the reader to look at the background page for more details.

This project is an offshoot of Stuart Conner's TMS9995 breadboard computer.

Basically this is a breadboard having the following:

  • TMS9995 microprocessor running from a 12MHz crystal (3MHz machine cycles)
  • 512K SRAM AS6C4008-55PCN
  • 256K FLASH ROM Pm29F002T
  • TMS9901 parallel IO port and interrupt controller
  • TMS9902 UART

All of the above is wired to a basic Xilinx Spartan 6 FPGA board, featuring XC6SLX9 FPGA and FTDI FT232R UART to USB chip.

Project background discussion, how this came to be. The background also has some pictures of the mess of wires this thing is.

Currently being added: SD card interface.

Memory map after reset

After reset paging is disabled.

Address range Device
0000..7FFF Bottom 32K of Flash ROM
8000..EFFF SRAM addresses 32K to 60K
F000..F0FB TMS9995 internal RAM
F0FC..FF2F SRAM roughly 60K to 64K
FF30..FF3F SPI controller
FF40..FF4F Memory page registers implemented by the FPGA
FF50..FF5F Test register, readonly, returns 5A
FF60..FFF9 SRAM
FFFA..FFFB TMS9995 decrementer
FFFC..FFFF TMS9995 NMI Workspace and PC in TMS9995 internal RAM

Memory map when paging enabled

There are 16 4K pages controlled by map registers FF40..FF4F. The internal registers and memory of the TMS9995 do not move, they always overlay what is externally mapped.

Page registers MSB Bits 6..0
0=SRAM selected, 1=ROM selected Page number in the respective device
The page number (7 bits) correspond to address bits A18 to A12 on the memory chips.

Memory page register at FF40 controls memory the first 4K range (0000..0FFF), FF41 the second range (1000..1FFF) and so on.

CRU IO Map

Address range Device
0000..003F TMS9902 UART
0040..007F TMS9901
0140..0147 Memory control register in the FPGA, "flag_reg"

flag_reg.

  • Bit 0 (CRU >140) when zero, the first 32K of address space is occupied by bottom 32K of ROM.
  • Bit 1 (CRU >141) when one, enables memory paging functions of the FPGA.

Both bits are zero after reset, thus ROM is enabled and paging disabled initially.

Clone this wiki locally