This project implements a 4-Bit Arithmetic Logic Unit (ALU) using Verilog HDL. The ALU is a combinational circuit capable of performing arithmetic, logical, and shift operations based on a 3-bit control signal (sel). The design was simulated and verified using ModelSim as part of the VLSI Internship Program conducted by Vedupskilling Pvt. Ltd.
- 4-bit combinational ALU
- 8 different operations
- Carry-out support for arithmetic operations
- Fully verified using a Verilog testbench
- ModelSim waveform validation
| sel | Operation |
|---|---|
| 000 | Addition |
| 001 | Subtraction |
| 010 | AND |
| 011 | OR |
| 100 | XOR |
| 101 | NOT |
| 110 | Shift Left |
| 111 | Shift Right |
- Verilog HDL
- ModelSim Intel FPGA Starter Edition 10.5b
- Intel Quartus Prime Lite
- Windows 11
- alu_4bit.v
- alu_4bit_tb.v
- Project Report
- Block Diagram
- Flowchart
- Simulation Waveform
The design was successfully compiled and simulated in ModelSim. The waveform verifies all eight ALU operations using constant operands and different values of the selection signal.
- CPUs
- Microprocessors
- Embedded Systems
- FPGA Design
- Digital Signal Processing
Sai Sutej Vedula
B.Tech – Electronics and Communication Engineering
GITAM University Hyderabad
VLSI Internship Trainee
Vedupskilling Pvt. Ltd.