This project presents the design and implementation of cache compression using Verilog, one of the efficient data storage strategies to maximize storage capacity.From the results we can assure that data is compressed and achieved in efficient manner.But it can be improved by the complex algorithms like LZ77/LZ78 Compression,Deflate,etc. Implementation on FPGA gives as the practical uses or real time uses. verilog-based cache implementations offer a flexible and customizable approach to improving overall system efficiency and speed