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Merged
AnZhong24 merged 2 commits into from
Jun 9, 2026
Merged

[minor-cpu] Support CoreMark workloads. #440

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b64458f
[minor-cpu] Support CoreMark workloads.
Jun 8, 2026
693ece5
[codegen] Support PyCDE pass phase filtering.
Jun 9, 2026
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31 changes: 28 additions & 3 deletions examples/minor-cpu/src/br_pre_main.py
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Original file line number Diff line number Diff line change
Expand Up @@ -216,6 +216,7 @@ def bypass(bypass_reg, bypass_data, idx, value):

# This `is_memory` hack is to evade rust's overflow check.
addr = (result.bitcast(UInt(32)) - is_memory.select(offset_reg[0].bitcast(UInt(32)), UInt(32)(0))).bitcast(Bits(32))
addr_lsb = addr[0:1]
request_addr = is_memory.select(addr[2:2+depth_log-1].bitcast(UInt(depth_log)), UInt(depth_log)(0))

with Condition(memory_read):
Expand All @@ -229,12 +230,36 @@ def bypass(bypass_reg, bypass_data, idx, value):

with Condition(rd != Bits(5)(0)):
log("own x{:02} |", rd)


byte_wmask = Bits(32)(0x000000ff)
byte_wdata = Bits(24)(0).concat(b[0:7])
byte_wmask = (addr_lsb == Bits(2)(1)).select(Bits(32)(0x0000ff00), byte_wmask)
byte_wdata = (addr_lsb == Bits(2)(1)).select(Bits(16)(0).concat(b[0:7]).concat(Bits(8)(0)), byte_wdata)
byte_wmask = (addr_lsb == Bits(2)(2)).select(Bits(32)(0x00ff0000), byte_wmask)
byte_wdata = (addr_lsb == Bits(2)(2)).select(Bits(8)(0).concat(b[0:7]).concat(Bits(16)(0)), byte_wdata)
byte_wmask = (addr_lsb == Bits(2)(3)).select(Bits(32)(0xff000000), byte_wmask)
byte_wdata = (addr_lsb == Bits(2)(3)).select(b[0:7].concat(Bits(24)(0)), byte_wdata)

half_wmask = addr_lsb[1:1].select(Bits(32)(0xffff0000), Bits(32)(0x0000ffff))
half_wdata = addr_lsb[1:1].select(b[0:15].concat(Bits(16)(0)), Bits(16)(0).concat(b[0:15]))

is_half = signals.mem_size == Bits(2)(1)
is_byte = signals.mem_size == Bits(2)(2)
store_wmask = is_byte.select(byte_wmask, is_half.select(half_wmask, Bits(32)(0xffffffff)))
store_wdata = is_byte.select(byte_wdata, is_half.select(half_wdata, b))

dcache = SRAM(width=32, depth=1<<depth_log, init_file=data)
dcache.name = 'dcache'

dcache.build(we=memory_write, re=memory_read, wdata=b, addr=request_addr)
bound = memory.bind(rd = rd,result = signals.link_pc.select(pc0, result), mem_ext = signals.mem_ext)
dcache.build(we=memory_write, re=memory_read, wdata=store_wdata, addr=request_addr, wmask=store_wmask)
bound = memory.bind(
rd=rd,
result=signals.link_pc.select(pc0, result),
mem_size=signals.mem_size,
mem_unsigned=signals.mem_unsigned,
addr_lsb=addr_lsb,
is_mem_read=memory_read,
)
bound.async_called()

return rd , ex_valid ,exec_br_jump
Expand Down
17 changes: 11 additions & 6 deletions examples/minor-cpu/src/decoder.py
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Expand Up @@ -82,10 +82,14 @@ def decode_logic(inst):
assume(Bits(1)(0))

# Extract all the signals
# For now, write is always disabled.
memory = concat(eqs['sw'], eqs['lw'] | eqs['lbu'])
# [ unsigned (signed), byte(word) ]
mem_ext = concat(eqs['lbu'], eqs['lbu'])
is_load = eqs['lb'] | eqs['lh'] | eqs['lw'] | eqs['lbu'] | eqs['lhu']
is_store = eqs['sb'] | eqs['sh'] | eqs['sw']
memory = concat(is_store, is_load)

mem_size = Bits(2)(0)
mem_size = (eqs['lh'] | eqs['lhu'] | eqs['sh']).select(Bits(2)(1), mem_size)
mem_size = (eqs['lb'] | eqs['lbu'] | eqs['sb']).select(Bits(2)(2), mem_size)
mem_unsigned = eqs['lbu'] | eqs['lhu']

# BInst and JInst are designed for branches.
is_branch = is_type[BInst] | is_type[JInst] | eqs['jalr'] | eqs['mret']
Expand Down Expand Up @@ -142,10 +146,11 @@ def decode_logic(inst):
rd_valid=rd_valid,
imm=imm,
imm_valid=imm_valid,
mem_size=mem_size,
mem_unsigned=mem_unsigned,
is_pc_calc = is_pc_calc,
csr_read=csr_read,
csr_write=csr_write,
csr_calculate=csr_calculate,
is_zimm = is_zimm,
is_mepc = is_mepc,
mem_ext = mem_ext)
is_mepc = is_mepc)
12 changes: 11 additions & 1 deletion examples/minor-cpu/src/instructions.py
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Original file line number Diff line number Diff line change
Expand Up @@ -235,17 +235,23 @@ class RV32I_ALU:

('add' , (0b0110011, 0b000, 0b0000000, RV32I_ALU.ALU_ADD), RInst),
('sub' , (0b0110011, 0b000, 0b0100000, RV32I_ALU.ALU_SUB), RInst),
('xor' , (0b0110011, 0b100, 0b0000000, RV32I_ALU.ALU_XOR), RInst),
('or' , (0b0110011, 0b110, 0b0000000, RV32I_ALU.ALU_OR) , RInst),

('jalr' , (0b1100111, 0b000, RV32I_ALU.ALU_ADD, (RV32I_ALU.ALU_TRUE, False), None, None), IInst),
('addi' , (0b0010011, 0b000, RV32I_ALU.ALU_ADD, None, None, None), IInst),


('lb' , (0b0000011, 0b000, RV32I_ALU.ALU_ADD, None, None, None), IInst),
('lh' , (0b0000011, 0b001, RV32I_ALU.ALU_ADD, None, None, None), IInst),
('lw' , (0b0000011, 0b010, RV32I_ALU.ALU_ADD, None, None, None), IInst),
('lbu' , (0b0000011, 0b100, RV32I_ALU.ALU_ADD, None, None, None), IInst),
('lhu' , (0b0000011, 0b101, RV32I_ALU.ALU_ADD, None, None, None), IInst),

('ebreak', (0b1110011, 0b000, RV32I_ALU.ALU_NONE, None,0b000000000001,None), IInst),

('sb' , (0b0100011, 0b000, RV32I_ALU.ALU_ADD), SInst),
('sh' , (0b0100011, 0b001, RV32I_ALU.ALU_ADD), SInst),
('sw' , (0b0100011, 0b010, RV32I_ALU.ALU_ADD), SInst),

# mn, opcode, funct3,cmp, flip
Expand All @@ -263,6 +269,7 @@ class RV32I_ALU:

('slli' , (0b0010011, 0b001, RV32I_ALU.ALU_SLL, None, None , 0b000000), IInst),
('sll' , (0b0110011, 0b001, 0b0000000, RV32I_ALU.ALU_SLL), RInst),
('slt' , (0b0110011, 0b010, 0b0000000, RV32I_ALU.ALU_CMP_LT), RInst),
('srai' , (0b0010011, 0b101, RV32I_ALU.ALU_SRA, None,None , 0b010000), IInst),#signed
('srli' , (0b0010011, 0b101, RV32I_ALU.ALU_SRA_U, None, None , 0b000000), IInst),#0
('sltu' , (0b0110011, 0b011, 0b0000000, RV32I_ALU.ALU_CMP_LTU), RInst),
Expand Down Expand Up @@ -300,6 +307,10 @@ class RV32I_ALU:
imm_valid=Bits(1),
# memory[0:0] is read, and memory[1:1] is write.
memory=Bits(2),
# memory access width: 0=word, 1=halfword, 2=byte.
mem_size=Bits(2),
# unsigned load flag for subword loads.
mem_unsigned=Bits(1),
# bit vector of ALU operations, which result should be selected.
alu=Bits(RV32I_ALU.CNT),
# bit vector of conditions, which should be selected to write or branch.
Expand All @@ -313,7 +324,6 @@ class RV32I_ALU:
is_offset_br=Bits(1),
# should we link the pc to rd
link_pc=Bits(1),
mem_ext=Bits(2),
)

#TODO(@were): Add `SInst` to the supported types later.
Expand Down
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