Fix mispelled signals and missing pins#2
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cfuguet wants to merge 8 commits intoThalesSiliconSecurity:pr/master_candidate_initial_oldfrom
Open
Fix mispelled signals and missing pins#2cfuguet wants to merge 8 commits intoThalesSiliconSecurity:pr/master_candidate_initial_oldfrom
cfuguet wants to merge 8 commits intoThalesSiliconSecurity:pr/master_candidate_initial_oldfrom
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Thanks for your fixes, I think I need to check also FPGA Top. |
yanicasa
changed the base branch from
pr/master_candidate_initial
to
pr/master_candidate_initial_old
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When compiling with Verilator, it alerts about different errors. Some of these are fixed in this PR.